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- Thomas, HS, et al.
(author)
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- 2019
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swepub:Mat__t
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- Ademuyiwa, Adesoji O., et al.
(author)
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Determinants of morbidity and mortality following emergency abdominal surgery in children in low-income and middle-income countries
- 2016
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In: BMJ Global Health. - : BMJ Publishing Group Ltd. - 2059-7908. ; 1:4
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Journal article (peer-reviewed)abstract
- Background: Child health is a key priority on the global health agenda, yet the provision of essential and emergency surgery in children is patchy in resource-poor regions. This study was aimed to determine the mortality risk for emergency abdominal paediatric surgery in low-income countries globally.Methods: Multicentre, international, prospective, cohort study. Self-selected surgical units performing emergency abdominal surgery submitted prespecified data for consecutive children aged <16 years during a 2-week period between July and December 2014. The United Nation's Human Development Index (HDI) was used to stratify countries. The main outcome measure was 30-day postoperative mortality, analysed by multilevel logistic regression.Results: This study included 1409 patients from 253 centres in 43 countries; 282 children were under 2 years of age. Among them, 265 (18.8%) were from low-HDI, 450 (31.9%) from middle-HDI and 694 (49.3%) from high-HDI countries. The most common operations performed were appendectomy, small bowel resection, pyloromyotomy and correction of intussusception. After adjustment for patient and hospital risk factors, child mortality at 30 days was significantly higher in low-HDI (adjusted OR 7.14 (95% CI 2.52 to 20.23), p<0.001) and middle-HDI (4.42 (1.44 to 13.56), p=0.009) countries compared with high-HDI countries, translating to 40 excess deaths per 1000 procedures performed.Conclusions: Adjusted mortality in children following emergency abdominal surgery may be as high as 7 times greater in low-HDI and middle-HDI countries compared with high-HDI countries. Effective provision of emergency essential surgery should be a key priority for global child health agendas.
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- Alzaher, H. A., et al.
(author)
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A CMOS fully balanced second-generation current conveyor
- 2003
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In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print). - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7130 .- 1558-125X. ; 50:6, s. 278-287
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Journal article (peer-reviewed)abstract
- The design and implementation of a high performance CMOS fully balanced second-generation current conveyor (FBCCII) is presented. The proposed circuit is essential to extend the use of the CCII based circuits to integrated circuits (ICs) applications. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA). A low power class AB circuit realization is implemented in a 1.2-mum CMOS technology and its different characteristics are measured. Design examples of realizing fully balanced variable gain amplifiers (VGAs) and a bandpass filter based on the proposed FBCCII are given. Experimental results of the proposed circuits are included.
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- Alzaher, H. A., et al.
(author)
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A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers
- 2002
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In: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:1, s. 27-37
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Journal article (peer-reviewed)abstract
- A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.
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- Alzaher, H. A., et al.
(author)
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CMOS digitally programmable filter for multi-standard wireless receivers
- 2000
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In: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 36:2, s. 133-135
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Journal article (peer-reviewed)abstract
- A technique for designing digitally programmable CMOS integrated filters for multi-standard wireless receivers is presented. The technique exhibits the wide frequency range of the transconductance amplifier filters while offering improved linearity. It utilises digitally controlled current followers to provide precise frequency characteristics that can be tuned over a wide range. A digitally tuned lowpass filter is designed for implementing the channel-select filter in the baseband chain of a multi-standard CMOS wireless receiver. Simulation and experimental results obtained from a 1.2 mu m chip show a programmable frequency response covering the IS-54, GSM, IS-95 and WCDMA wireless standards.
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- Alzaher, H. A., et al.
(author)
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CMOS fully differential second-generation current conveyor
- 2000
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In: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 36:13, s. 1095-1096
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Journal article (peer-reviewed)abstract
- The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 mu m CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented.
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- Elwan, H., et al.
(author)
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A CMOS Norton amplifier-based digitally controlled VGA for low-power wireless applications
- 2001
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In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print). - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7130 .- 1558-125X. ; 48:3, s. 245-254
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Journal article (peer-reviewed)abstract
- A CMOS variable-gain amplifier (VGA) for use in the baseband section of integrated wireless receivers is presented. The VGA circuit is based on a new CMOS realization of the Norton transresistance amplifier. The proposed CMOS realization operates from a 3-V supply voltage with rail-to-rail swing and class AB input and output stages. The standby current of the class AB stages employed can be accurately controlled, leading to a low power consumption, nonslew-rate-limited response. The VGA circuit provides a precise process-independent gain control range of 30 dB with 1-dB gain step. The circuit uses current division techniques to provide an area-efficient B-bit digital offset trimming capability Experimental results from a test chip fabricated through MOSIS are provided.
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- Elwan, H., et al.
(author)
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CMOS low power baseband chain for a GSM/DECT multistandard receiver
- 2002
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In: IEE Proceedings - Circuits Devices and Systems. - : Institution of Engineering and Technology (IET). - 1350-2409 .- 1359-7000. ; 149:06-maj, s. 337-347
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Journal article (peer-reviewed)abstract
- A CMOS low power baseband chain for an integrated GSM/DECT multistandard receiver is presented. The chain uses a low power class AB digitally controlled filter and variable gain amplifier blocks to provide a low power, DSP controllable design solution. The chain and the building blocks are fabricated using standard N-well CMOS technology. Measurement results indicate that the chain can operate in GSM or DECT mode with a total standby current consumption less than 1.5 mA, while providing a gain control range from -6 dB to 23 dB in 1 dB steps. The chain achieves an input referred noise less than 31 nV/rootHz and an out-of-band IIP3 of more than 30 dBm.
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