| 1. |
- Abadie, J., et al.
(author)
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Search for Gravitational Waves Associated with Gamma-Ray Bursts during LIGO Science Run 6 and Virgo Science Runs 2 and 3
- 2012
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In: Astrophysical Journal. - 0004-637X. ; 760:1
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Journal article (peer-reviewed)abstract
- We present the results of a search for gravitational waves associated with 154 gamma-ray bursts (GRBs) that were detected by satellite-based gamma-ray experiments in 2009-2010, during the sixth LIGO science run and the second and third Virgo science runs. We perform two distinct searches: a modeled search for coalescences of either two neutron stars or a neutron star and black hole, and a search for generic, unmodeled gravitational-wave bursts. We find no evidence for gravitational-wave counterparts, either with any individual GRB in this sample or with the population as a whole. For all GRBs we place lower bounds on the distance to the progenitor, under the optimistic assumption of a gravitational-wave emission energy of 10(-2) M-circle dot c(2) at 150 Hz, with a median limit of 17 Mpc. For short-hard GRBs we place exclusion distances on binary neutron star and neutron-star-black-hole progenitors, using astrophysically motivated priors on the source parameters, with median values of 16 Mpc and 28 Mpc, respectively. These distance limits, while significantly larger than for a search that is not aided by GRB satellite observations, are not large enough to expect a coincidence with a GRB. However, projecting these exclusions to the sensitivities of Advanced LIGO and Virgo, which should begin operation in 2015, we find that the detection of gravitational waves associated with GRBs will become quite possible.
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| 2. |
- Buiu, O., et al.
(author)
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Extracting the relative dielectric constant for "high-k layers" from CV measurements : Errors and error propagation
- 2007
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In: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:4-5, s. 678-681
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Journal article (peer-reviewed)abstract
- The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., kappa value) from capacitance-voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-rc dielectric and the silicon substrate is a factor that affects - in general - the assessment of the electrical data, as well as the extraction of rc. A methodology which accounts for this transition layer and the errors related to other parameters involved in the k value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO2/SiOx/Si structures produced in different conditions.
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| 3. |
- Cherkaoui, K., et al.
(author)
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High-k/InGaAs interface defects at cryogenic temperature
- 2023
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In: Solid-State Electronics. - 0038-1101. ; 207
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Journal article (peer-reviewed)abstract
- Oxide defects in the high-k/InGaAs MOS system are investigated. The behaviour of these traps is explored from room temperature down to 10 K. This study reveals that the exchange of free carriers between oxide states and either the conduction or the valence band is strongly temperature dependant. The capture and emission of electrons is strongly suppressed at 10 K as demonstrated by the collapse of the capacitance frequency dispersion in accumulation for n-InGaAs MOS devices, though hysteresis in the C-V sweeps is still present at 10 K. Phonon assisted tunnelling processes are considered in the simulation of electrical characteristics. The simulated data match very well the experimental characteristics and provide energy and spatial mapping of oxide defects. The multi phonon theory also help explain the impedance data temperature dependence. This study also reveals an asymmetry in the free carrier trapping between n and p type devices, where hole trapping is more significant at 10 K.
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| 4. |
- Engstrom, O., et al.
(author)
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Navigation aids in the search for future high-k dielectrics : Physical and electrical trends
- 2007
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In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 622-626
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Journal article (peer-reviewed)abstract
- From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.
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| 5. |
- Engström, Olof, 1943, et al.
(author)
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A generalised methodology for oxide leakage current metric
- 2008
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In: Proceeding of 9th European Workshop on Ultimate Integration of Silicon (ULIS), Udine, Italy. - 9781424417308 ; , s. 167-
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Conference paper (peer-reviewed)abstract
- From calculations of semiconductor interfacecharge, oxide voltage and tunneling currents for MOSsystems with equivalent oxide thickness (EOT) in therange of 1 nm, rules are suggested for making itpossible to compare leakage quality of different oxideswith an accuracy of a factor 2 – 3 if the EOT is known.The standard procedure suggested gives considerablybetter accuracy than the commonly used method todetermine leakage at VFB+1V for n-type and VFB-1V forp-type substrates.
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| 6. |
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| 7. |
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| 8. |
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| 9. |
- Gomeniuk, Y. Y., et al.
(author)
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Electrical properties of high-k LaLuO3 gate oxide for SOI MOSFETs
- 2011
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In: 6th International Workshop on Semiconductor-on-Insulator Materials and Devices. - 9783037851784 ; , s. 87-93
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Conference paper (peer-reviewed)abstract
- The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-? LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO 3/Si interface is presented and typical maxima of 1.2×10 11 eV-1cm-2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 μm and 50 μm, respectively) are presented. The front channel mobility appeared to be 126 cm2V -1s-1 and 70 cm2V-1s-1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.
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| 10. |
- Gottlob, H. D. B., et al.
(author)
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Gd silicate : A high-k dielectric compatible with high temperature annealing
- 2009
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In: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
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Journal article (peer-reviewed)abstract
- The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
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| 11. |
- Gottlob, H. D. B., et al.
(author)
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Gentle FUSI NiSi metal gate process for high-k dielectric screening
- 2008
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 85:10, s. 2019-2021
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Journal article (peer-reviewed)abstract
- In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).
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| 12. |
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| 13. |
- Hurley, P. K., et al.
(author)
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Interface defects in HfO2, LaSiOx, and Gd2O3 high-k/metal-gate structures on silicon
- 2008
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In: Journal of the Electrochemical Society. - : The Electrochemical Society. - 0013-4651 .- 1945-7111. ; 155:2, s. G13-G20
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Journal article (peer-reviewed)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.
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| 14. |
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| 15. |
- Hurley, P.K., et al.
(author)
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Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/MetalGate Structures on Silicon
- 2008
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In: J. Electrochem. Soc.. ; 155:2, s. G13-G20
-
Journal article (peer-reviewed)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (>1×10^11 cm−2) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal–insulator–silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H2/N2 annealing following the gate stack formation, reveals a peak density (~2×10^12 cm−2 eV−1 to ~1×10^13 cm−2 eV−1) at 0.83–0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si(100). The characteristic peak in the interface state density (0.83–0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (Pbo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H2/N2) annealing over the temperature range 350–555°C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed.
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| 16. |
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| 17. |
- Lu, Y., et al.
(author)
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Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors
- 2009
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In: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 352-355
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Journal article (peer-reviewed)abstract
- With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.
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| 18. |
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| 19. |
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| 20. |
- Raeissi, Bahman, 1979, et al.
(author)
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High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
- 2007
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In: ESSDERC 2007. - 9781424411238 ; , s. 283-286
-
Conference paper (peer-reviewed)abstract
- Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd(2)O(3) prepared by MBE and ALD, and for HfO(2) prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.
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| 21. |
- Raeissi, Bahman, 1979, et al.
(author)
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High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
- 2008
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In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:9, s. 1274-1279
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Journal article (peer-reviewed)abstract
- Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 preparedby molecular beam epitaxy (MBE) and atomic layer deposition (ALD), and for HfO2 prepared byreactive sputtering, by measuring the frequency dependence of Metal Oxide Semiconductor (MOS) capacitance.The capture cross sections are found to be thermally activated and to increase steeply with theenergy depth of the interface electron states. The methodology adopted is considered useful for increasingthe understanding of high-k-oxide/silicon interfaces.
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| 22. |
- Schmidt, M., et al.
(author)
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Impact of H-2/N-2 annealing on interface defect densities in Si(100)/SiO2/HfO2/TiN gate stacks
- 2005
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 80, s. 70-73
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Journal article (peer-reviewed)abstract
- This paper reports on the influence of forming gas annealing (5%H-2/95%N-2) over the temperature range 350 degrees C-550 degrees C on the density of electrically active interface states in Si(100)/SiO2/HfO2/TiN gate stacks. Prior to forming gas annealing the distribution of interface states across the energy gap exhibits the electrical signature of the P-b0 dangling bond centre for the hydrogen free Si(100)/SiO2 interface. Forming gas annealing at 350 degrees C and 400 degrees C results in a reduction of the interface state density, with an increase in interface state density for forming gas anneals in the range 450 degrees C-550 degrees C. The effect of the cooling ambient for the forming gas anneal (N-2 or H-2/N-2) is also reported.
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