| 1. |
- Ang, Lay-Hong, et al.
(author)
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Modification of SOVA-based Algorithms for Efficient Hardware Implementation
- 2010
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In: IEEE 71st Vehicular Technology Conference (VTC 2010-Spring), 2010. - 1550-2252. ; , s. 1-5
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Conference paper (peer-reviewed)abstract
- In this paper, a modified soft-output Viterbi algorithm (SOVA) is presented to enable efficient hardware implementation. The forward-only processing of the SOVA has an inherent lower latency than forward-backward algorithms such as BCJR and its offspring, which are commonly used in iterative decoders. Thus, SOVA-based architectures require less parallelization and therefore hardware for the same data throughput. A simplification is proposed to the Battail rule ( BR) SOVA to approximate the concurrent path reliability values with the corresponding metric differences. This simplified BR-SOVA (SB-SOVA) performs close to max-log-MAP. Furthermore, a novel hybrid decoding architecture is proposed that combines the simplicity of the original Hagenauer rule and the performance-preserving properties of the SB-SOVA to trade implementation complexity for decoding performance. The hybrid approach is evaluated with practical link-level simulations of the downlink data channel in LTE Rel-8.
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| 2. |
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| 3. |
- Hedberg, Hugo, et al.
(author)
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Teaching digital ASIC design to students with heterogeneoms previous knowledge
- 2005
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In: Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education. - 0769523749 ; , s. 15-16
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Conference paper (peer-reviewed)abstract
- This paper describes a MSc level digital ASIC project course. The majority of the course participants are international students, having a wide spread in previous knowledge in the field of digital HW-design. A course outline adapting to this fact has been developed, changing from one joint VLSI project towards smaller individual projects. The diversity in previous knowledge is evened out by adding lectures regarding design methodology and used EDA-tools, and making the first part of the course purely, laboratory. To enhance and highlight different aspects of HDL-design, mandatory assignments allow the students to gradually take command over the complete design flow. As a result, comprehension of digital ASIC design is increased among the students and course administration is reduced.
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| 4. |
- Kamuf, Matthias, et al.
(author)
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A hardware efficiency analysis for simplified trellis decoding blocks
- 2005
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In: [Host publication title missing]. - 1520-6130. - 0780393333 ; 2005, s. 128-132
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Conference paper (peer-reviewed)abstract
- Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.
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| 5. |
- Kamuf, Matthias, et al.
(author)
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A simplified computational kernel for trellis-based decoding
- 2004
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In: IEEE Communications Letters. - 1089-7798. ; 8:3, s. 156-158
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Journal article (peer-reviewed)abstract
- A simplified branch metric and add-compare-select (ACS) unit is presented for use in trellis-based decoding architectures. The simplification is based on a complementary property of best feedforward and some systematic feedback encoders. As a result, one adder is saved in every other ACS unit. Furthermore, only half the branch metrics have to be calculated. It is shown that this simplification becomes especially beneficial for rate 1/2 convolutional codes. Consequently, area and power consumption will be reduced in a hardware implementation.
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| 6. |
- Kamuf, Matthias, et al.
(author)
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A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
- 2008
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In: Proceedings, Norchip Conference. ; , s. 137-141
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Conference paper (peer-reviewed)abstract
- This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
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| 7. |
- Kamuf, Matthias, et al.
(author)
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Architectural considerations for rate-flexible trellis processing blocks
- 2005
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In: 2005 IEEE 16th International Symposium on Personal, Indoor and Mobile Radio Communications. - 9783800729098 ; , s. 1076-1080
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Conference paper (peer-reviewed)abstract
- A flexible channel decoding platform should be able to operate in varying communication scenarios, and different code rates have to be supported. Therefore, we present a framework that allows efficient processing of rate-flexible trellises. Using a fundamental computational unit for trellis-based decoding, formal principles are obtained to emulate more complex trellises. In a design example, such a computational block supports both rate 1/c convolutional codes and set partition codes with subset selectors of rate 2/3. Synthesis results show the hardware requirements for two different architectural approaches
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| 8. |
- Kamuf, Matthias, et al.
(author)
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Area and power efficient trellis computational blocks in 0.13μm CMOS
- 2005
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In: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 344-347
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Conference paper (peer-reviewed)abstract
- Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption
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| 9. |
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| 10. |
- Kamuf, Matthias, et al.
(author)
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Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
- 2010
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In: Microprocessors and Microsystems. - : Elsevier BV. - 0141-9331. ; 34:2010, s. 129-137
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Journal article (peer-reviewed)abstract
- This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
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| 11. |
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| 12. |
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| 13. |
- Kamuf, Matthias, et al.
(author)
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Optimization and implementation of a Viterbi decoder under flexibility constraints
- 2008
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In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 55:8, s. 2411-2422
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Journal article (peer-reviewed)abstract
- This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13- $mu{hbox {m}}$ CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.
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| 14. |
- Kamuf, Matthias, et al.
(author)
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Providing flexibility in a convolutional encoder
- 2003
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In: Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (Cat. No.03CH37430). - 0780377613 ; , s. 272-275
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Conference paper (peer-reviewed)abstract
- In future radio systems, flexible coding and decoding architectures will be required. In case of the latter, implementing architectural flexibility with regard to low power issues is a challenging task. The flexible encoding platform in this paper is a first step toward this envisioned decoder. It generates a wide class of codes, starting with convolutional codes. As an extension to this, turbo codes will be included by adding an interleaver. At this prototyping stage, the system is implemented on an FPGA. The decision to choose the observer canonical form is defended by a thorough investigation of its critical path properties. Proper configuration allows code rates of b/c, b=1 ... 15, c=2 ... 16, b
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| 15. |
- Kamuf, Matthias, et al.
(author)
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Survivor path processing in Viterbi decoders using register exchange and traceforward
- 2007
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In: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 54:6, s. 537-541
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Journal article (peer-reviewed)abstract
- This paper proposes a new class of hybrid VLSI architectures for survivor path processing to be used in Viterbi decoders. The architecture combines the benefits of register exchange and trace-forward algorithms, that is, low memory requirement and latency versus implementation efficiency. Based on a structural comparison, it becomes evident that the architecture can be efficiently applied to codes with a larger number of states where usually trace-back-based architectures, which increase latency, are dominant.
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| 16. |
- Kamuf, Matthias
(author)
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Trellis Decoding: From Algorithm to Flexible Architectures
- 2007
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Doctoral thesis (other academic/artistic)abstract
- Trellis decoding is a popular method to recover encoded information corrupted during transmission over a noisy channel. Prominent members of this class of decoding algorithms are the Viterbi algorithm, which provides maximum likelihood estimates, and the BCJR algorithm, which is a maximum a posteriori estimator commonly used in iterative decoding. In this thesis, the Viterbi algorithm is chosen since it provides a good trade-off between achievable coding gain and implementation complexity. This is the basis for considerations on simplified, hybrid, and, most importantly, flexible VLSI architectures. Algorithm simplifications are necessary to reduce the computational burden laid on an implementation platform. In our work on trellis decoding blocks, a simplification that lowers the number of arithmetic operations is derived and evaluated. By using a complementary code property, the arithmetic complexity of the main part on the Viterbi algorithm is reduced by 17%. Synthesized blocks show varying savings for cell area and estimated power consumption. A comparison to a competing simplification shows the advantage in a hardware implementation of our work for the important class of rate 1/2 convolutional codes. Hybrid architectures try to combine benefits of several approaches to lower the drawbacks of the individual contributors. For survivor path processing in Viterbi decoders, a new hybrid approach is proposed. A low-latency algorithm, whose implementation complexity quickly increases with the number of trellis states, is combined with a scalable RAM-based method. As a result, the developed hybrid architecture exhibits a better latency-complexity behavior compared to other hybrid approaches. Flexible VLSI architectures to cover several communication standards become increasingly important as fabrication costs for microchips rise rapidly with every new process generation. In the context of flexible trellis decoding, earlier work mostly concentrated on varying encoder memory and thus the number of trellis states. This work studies the effects on hardware size and throughput introduced by flexibility if the code rate is varied. The investigation of a decoder for bandwidth-efficient codes, which was fabricated in a 0.13 um digital CMOS process and verified for functionality, distinguishes between task- and rate-flexibility. A comparison is carried out between flexible designs, which decode both convolutional and TCM codes and provide two or three transmission rates. It is concluded that the larger number of rates is more beneficial from a cost--flexibility viewpoint.
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| 17. |
- Rodrigues, Joachim, et al.
(author)
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A manual on ASIC front to back end design flow
- 2005
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In: [Host publication title missing]. - 0769523749 ; , s. 75-76
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Conference paper (peer-reviewed)abstract
- This paper presents a manual that covers the necessary design steps for a basic ASIC design flow. It is shown how the manual writing process is organized such that each chapter covers a certain step in the design flow. The manual has been written especially with practicality in mind and has been successfully applied to undergraduate and postgraduate teaching
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| 18. |
- Rupanagudi, Sudhir Rao, et al.
(author)
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Reducing computational complexity of branch metric calculations in a trellis decoder
- 2008
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Conference paper (peer-reviewed)abstract
- Trellis decoding is widely used, in this present day of communication and data storage, in a wide variety of applications such as decoding convolution codes, baseband detection for wireless systems and also to detect recorded data. This is achieved by implementing the Viterbi algorithm. This paper presents various methodologies of reducing the computational complexity of the branch metric unit in a trellis decoder. Further, a new methodology identified by us, which can be used to simplify the computations further, has been discussed. The adoption of this method, has been verified in a 0.13μ standard CMOS process, which shows 60% reduction in area as compared to the designs incorporating the existing methodologies.
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