| 1. |
- Ali, Mai, et al.
(author)
-
Autonomous Patient/Home Health Monitoring powered by Energy Harvesting
- 2017
-
In: Globecom 2017 - 2017 IEEE Global Communications Conference. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509050192
-
Conference paper (peer-reviewed)abstract
- This paper presents the design of an autonomous smart patient/home health monitoring system. Both patient physiological parameters as well as room conditions are being monitored continuously to insure patient safety. The sensors are connected on an IoT regime, where the collected data is wirelessly transferred to a nearby gateway which performs preliminary data analysis, commonly referred to as fog computing, to make sure emergency personnel and healthcare providers are notified in case patient being monitored is at risk. To achieve power autonomy three energy harvesting sources are proposed, namely, solar, RF and thermal. The design of the RF energy harvesting system is demonstrated, where novel multiband antenna is fabricated as well as an efficient RF-DC rectifier achieving maximum conversion efficiency of 84%. Finally, the sensor node is tested with different type of sensors and settings while being solely powered by a Photovoltaic (PV) solar cell.
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| 2. |
- Amin, Yasar, et al.
(author)
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Green wideband RFID tag antenna for supply chain applications
- 2012
-
In: IEICE Electronics Express. - : Institute of Electronics, Information and Communications Engineers (IEICE). - 1349-2543. ; 9:24, s. 1861-1866
-
Journal article (peer-reviewed)abstract
- In this paper, we demonstrate an RFID tag antenna manufactured by advanced inkjet printing technology on paper substrate using novel hole-matching technique for reducing the consumption of substrate material and conductive ink while attaining green RFID tags. In-depth electromagnetic analysis is performed methodologically for optimizing the parameters that effectuate the antenna dimensions. The antenna design is optimized for consistent wideband performance and extended read range throughout the complete UHF RFID band (860-960MHz), while exhibiting benchmarking results when n across cardboard cartons filled with metal or water containing objects.
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| 3. |
- Amin, Yasar, et al.
(author)
-
Performance-optimized Printed Wideband RFID Antenna and Environmental Impact Analysis
- 2024
-
In: ETRI Journal. - Korea : ETRI. - 1225-6463 .- 2233-7326.
-
Journal article (peer-reviewed)abstract
- This paper presents performance optimized RFID tag antenna, developed by using commercially accessible paper substrates and advanced inkjet printing process to guarantee mechanical flexibility and ultra-low production costs. The proposed antenna structure can endure the variations which emerge in electromagnetic properties of paper substrate due to varying environmental effects. Hole-matching technique is implemented to eliminate the matching network for reducing the consumption of conductive ink. The proposed structure is uniquely evaluated by demonstrating, sustainability and environmental impact analysis that validate the potential for ultra-low cost mass production of RFID tags for future generation of organic electronics. The antenna performance is assessed for cardboard cartons exclusively containing metal cans and water bottles. The experimental characterization of the proposed antenna endorses the wider bandwidth to cover UHF RFID ISM band (860-960MHz), which empowers its usage throughout the globe for supply chain applications. The improved design effectuates return loss of better than -15dB over a wide frequency range while exhibiting outstanding readability from 10.1 meters.
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| 4. |
- Azimi, Iman, et al.
(author)
-
Internet of things for remote elderly monitoring : a study from user-centered perspective
- 2017
-
In: Journal of Ambient Intelligence and Humanized Computing. - : SPRINGER HEIDELBERG. - 1868-5137 .- 1868-5145. ; 8:2, s. 273-289
-
Journal article (peer-reviewed)abstract
- Improvements in life expectancy achieved by technological advancements in the recent decades have increased the proportion of elderly people. Frailty of old age, susceptibility to diseases, and impairments are inevitable issues that these senior adults need to deal with in daily life. Recently, there has been an increasing demand on developing elderly care services utilizing novel technologies, with the aim of providing independent living. Internet of things (IoT), as an advanced paradigm to connect physical and virtual things for enhanced services, has been introduced that can provide significant improvements in remote elderly monitoring. Several efforts have been recently devoted to address elderly care requirements utilizing IoT-based systems. Nevertheless, there still exists a lack of user-centered study from an all-inclusive perspective for investigating the daily needs of senior adults. In this paper, we study the IoT-enabled systems tackling elderly monitoring to categorize the existing approaches from a new perspective and to introduce a hierarchical model for elderly-centered monitoring. We investigate the existing approaches by considering the elderly requirements at the center of the attention. In addition, we evaluate the main objectives and trends in IoT-based elderly monitoring systems in order to pave the way for future systems to improve the quality of elderly's life.
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| 5. |
- Ebrahimi, Masoumeh, et al.
(author)
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Partitioning methods for unicast/multicast traffic in 3D NoC architecture
- 2010
-
In: Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 127-132
-
Conference paper (peer-reviewed)abstract
- As the scale of integration grows, the interconnection problem becomes one of the major design considerations of Multi Processor System on Chip (MPSoC). In recent years, many researchers have conducted studies on 3D IC designs stacking multiple layers on top of each other. In order to decrease the transmission delay of unicast/multicast messages in a network based multicore system, the network is divided into several partitions. In this paper, we first introduce a novel idea of balanced partitioning that allows the network to be partitioned effectively. Then, we propose a set of partitioning approaches each with a different level of efficiency. In addition, we present an advantageous method based on the idea of balanced partitioning to provide a high degree of parallelism with a considerable reduction of packet delay in unicast/multicast traffic. Simulations are provided to evaluate and compare the performance of proposed methods.
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| 6. |
- Ebrahimi, Masoumeh, et al.
(author)
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Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing
- 2014
-
In: IEEE Transactions on Computers. - 0018-9340 .- 1557-9956. ; 63:3, s. 718-733
-
Journal article (peer-reviewed)abstract
- Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in ChipMultiprocessors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and invarious parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at thehardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs,each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore theefficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose theMinimal and Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show thatan advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the networkuntil all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsetsand the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performanceimprovement across all workloads while performance can be further improved by utilizing the MAR algorithm. Nineteen percent averageand 42 percent maximum latency reduction are obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.
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| 7. |
- Ebrahimi, Masoumeh, et al.
(author)
-
Performance Analysis of 3D NoCs Partitioning Methods
- 2010
-
In: IEEE Annual Symposium on VLSI, ISVLSI 2010. ; , s. 479-480
-
Conference paper (peer-reviewed)abstract
- 3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with short vertical ones. Achieving higher performance along with reducing the network latency can be obtained by utilizing an efficient communication protocol in 3D Networks-on-Chlp (NoCs). In this work, several unlcast/multicast partitioning methods are explained in order to And an advantageous method with low communication latency. Moreover, two factors of efficiency, unicast latency and multicast latency, are analyzed by analytical models. We also perform simulation to compare the efficiency of proposed methods. The results show that Mixed Partitioning method outperforms other methods in term of latency.
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| 8. |
- Farahnakian, Fahimeh, et al.
(author)
-
Adaptive Load Balancing in Learning-based Approaches for Many-core Embedded Systems
- 2014
-
In: Journal of Supercomputing. - : Springer Science and Business Media LLC. - 0920-8542 .- 1573-0484. ; 68:3, s. 1214-1234
-
Journal article (peer-reviewed)abstract
- Adaptive routing algorithms improve network performance by distributingtraffic over the whole network. However, they require congestion information to facilitateload balancing. To provide local and global congestion information, we proposea learning method based on dual reinforcement learning approach. This informationcan be dynamically updated according to the changing traffic condition in the networkby propagating data and learning packets. We utilize a congestion detection methodwhich updates the learning rate according to the congestion level. This method calculatesthe average number of free buffer slots in each switch at specific time intervalsand compares it with maximum and minimum values. Based on the comparison result,the learning rate sets to a value between 0 and 1. If a switch gets congested, the learningrate is set to a high value, meaning that the global information is more important thanlocal. In contrast, local is more emphasized than global information in non-congestedswitches. Results show that the proposed approach achieves a significant performanceimprovement over the traditional Q-routing, DRQ-routing, DBAR and Dynamic XYalgorithms.
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| 9. |
- Farahnakian, Fahimeh, et al.
(author)
-
Bi-LCQ: A Low-weight Clustering-based Q-learning Approach for NoCs
- 2014
-
In: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 38:1, s. 64-75
-
Journal article (peer-reviewed)abstract
- Network congestion has a negative impact on the performance of on-chip networks due to the increasedpacket latency. Many congestion-aware routing algorithms have been developed to alleviate trafficcongestion over the network. In this paper, we propose a congestion-aware routing algorithm basedon the Q-learning approach for avoiding congested areas in the network. By using the learning method,local and global congestion information of the network is provided for each switch. This information canbe dynamically updated, when a switch receives a packet. However, Q-learning approach suffers fromhigh area overhead in NoCs due to the need for a large routing table in each switch. In order to reducethe area overhead, we also present a clustering approach that decreases the number of routing tablesby the factor of 4. Results show that the proposed approach achieves a significant performance improvementover the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms.
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| 10. |
- Gia, Tuan Nguyen, et al.
(author)
-
IoT-Based Fall Detection System with Energy Efficient Sensor Nodes
- 2016
-
In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). - : IEEE conference proceedings. - 9781509010950
-
Conference paper (peer-reviewed)abstract
- Fall needs to be attentively considered due to its highly frequent occurrence especially with old people - up to one third of 65 and above year-old people around the world are risk of being injured due to falling. Furthermore, fall is a direct or indirect factor causing severe traumas such as brain injuries or bone fractures. However, timely medical attention might help to avoid serious consequences from a fall. A viable solution to solve this is an IoT-based system which takes advantage of wireless sensor networks, wearable devices, Fog and Cloud computing. To deliver sufficient degree of reliability, wearable devices working at the core of a fall detection system, are required to work for prolonged period of time. In this paper we investigate energy consumption of sensor nodes in an IoT-based fall detection system and present a design of a customized sensor node. In addition, we compare the customized sensor node with other sensor nodes, built on general purpose development boards. The results show that sensor nodes based on delicate customized devices are more energy efficient than the others based on general purpose devices while considering identical specification of micro-controller and memory capacity. Furthermore, our customized sensor node with energy efficiency selections can operate continuously up to 35 hours.
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| 11. |
- Haghbayan, Mohammad-Hashem, et al.
(author)
-
A Lifetime-Aware Runtime Mapping Approach for Many-core Systems in the Dark Silicon Era
- 2016
-
In: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE). - : IEEE conference proceedings. - 9783981537079 ; , s. 854-857
-
Conference paper (peer-reviewed)abstract
- In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach.
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| 12. |
- Haghbayan, Mohammad-Hashem, et al.
(author)
-
A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures
- 2016
-
In: IEEE Transactions on Computers. - : IEEE. - 0018-9340 .- 1557-9956. ; 65:3, s. 730-743
-
Journal article (peer-reviewed)abstract
- Aggressive technology scaling triggers novel challenges to the design of multi-/many-core systems, such as limited power budget and increased reliability issues. Today's many-core systems employ dynamic power management and runtime mapping strategies trying to offer optimal performance while fulfilling power constraints. On the other hand, due to the reliability challenges, online testing techniques are becoming a necessity in current and near future technologies. However, state-of-the-art techniques are not aware of the other power/performance requirements. This paper proposes a power-aware non-intrusive online testing approach for many-core systems. The approach schedules software based self-test routines on the various cores during their idle periods, while honoring the power budget and limiting delays in the workload execution. A test criticality metric, based on a device aging model, is used to select cores to be tested at a time. Moreover, power and reliability issues related to the testing at different voltage and frequency levels are also handled. Extensive experimental results reveal that the proposed approach can i) efficiently test the cores within the available power budget causing a negligible performance penalty, ii) adapt the test frequency to the current cores' aging status, and iii) cover available voltage and frequency levels during the testing.
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| 13. |
- Haghbayan, Mohammad-Hashem, et al.
(author)
-
Adaptive Fault Simulation on Many-core Microprocessor Systems
- 2015
-
In: PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS). - : IEEE Computer Society. - 9781509003129 ; , s. 151-154
-
Conference paper (peer-reviewed)abstract
- Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platfonn, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.
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| 14. |
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| 15. |
- Jiang, Mingzhe, et al.
(author)
-
IoT-based Remote Facial Expression Monitoring System with sEMG Signal
- 2016
-
In: 2016 IEEE SENSORS APPLICATIONS SYMPOSIUM (SAS 2016) PROCEEDINGS. - : IEEE. - 9781479972500 ; , s. 211-216
-
Conference paper (peer-reviewed)abstract
- Biopotentials including Electrocardiography (ECG), Electromyography (EMG) and Electroencephalography (EEG) measure the activity of heart, muscles and brain, respectively. They can be used for noninvasive diagnostic applications, assistance in rehabilitation medicine and human-computer interaction. The concept of Internet of Things (IoT) can bring added value to applications with biopotential signals in healthcare and human-computer interaction by integrating multiple technologies such as sensors, wireless communication and data science. In this work, we present a wireless biopotentials remote monitoring and processing system. A prototype with the case study of facial expression recognition using four channel facial sEMG signals is implemented. A multivariate Gaussian classifier is trained offline from one person's surface EMG (sEMG) signals with four facial expressions: neutral, smile, frown and wrinkle nose. The presented IoT application system is implemented on the basis of an eight channel biopotential measurement device, Wi-Fi module as well as signal processing and classification provided as a Cloud service. In the system, the real-time sEMG data stream is filtered, feature extracted and classified within each data segment and the processed data is visualized in a browser remotely together with the classification result.
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| 16. |
- Kanduri, Anil, et al.
(author)
-
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications
- 2017
-
In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1063-8210 .- 1557-9999. ; 25:10, s. 2749-2762
-
Journal article (peer-reviewed)abstract
- Power capping techniques based on dynamic voltage and frequency scaling (DVFS) and power gating (PG) are oriented toward power actuation, compromising on performance and energy. Inherent error resilience of emerging application domains, such as Internet-of-Things (IoT) and machine learning, provides opportunities for energy and performance gains. Leveraging accuracy-performance tradeoffs in such applications, we propose approximation (APPX) as another knob for close-looped power management, to complement power knobs with performance and energy gains. We design a power management framework, APPEND+, that can switch between accurate and approximate modes of execution subject to system throughput requirements. APPEND+ considers the sensitivity of the application to error to make disciplined alteration between levels of APPX such that performance is maximized while error is minimized. We implement a power management scheme that uses APPX, DVFS, and PG knobs hierarchically. We evaluated our proposed approach over machine learning and signal processing applications along with two case studies on IoT-early warning score system and fall detection. APPEND+ yields 1.9x higher throughput, improved latency up to five times, better performance per energy, and dark silicon mitigation compared with the state-of-the-art power management techniques over a set of applications ranging from high to no error resilience.
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| 17. |
- Kanduri, Anil, et al.
(author)
-
Approximation Knob : Power Capping Meets Energy Efficiency
- 2016
-
In: 2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD). - New York, NY, USA : Institute of Electrical and Electronics Engineers (IEEE). - 9781450344661
-
Conference paper (peer-reviewed)abstract
- Power Capping techniques are used to restrict power consumption of computer systems to a thermally safe limit. Current many-core systems employ dynamic voltage and frequency scaling (DVFS), power gating (PG) and scheduling methods as actuators for power capping. These knobs are oriented towards power actuation, while the need for performance and energy savings are increasing in the dark silicon era. To address this, we propose approximation (APPX) as another knob for close-looped power management, lending performance and energy efficiency to existing power capping techniques. We use approximation in a pro-active way for long-term performance-energy objectives, complementing the short-term reactive power objectives. We implement an approximation-enabled power management framework, APPEND, that dynamically chooses an application with appropriate level of approximation from a set of variable accuracy implementations. Subject to the system dynamics, our power manager chooses an effective combination of knobs APPX, DVFS and PG, in a hierarchical way to ensure power capping with performance and energy gains. Our proposed approach yields 1.5x higher throughput, improved latency upto 5x, better performance per energy and dark silicon mitigation compared to state-of-the-art power management techniques over a set of applications ranging from high to no error resilience.
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| 18. |
- Kanduri, Anil, et al.
(author)
-
Dark Silicon Aware Runtime Mapping for Many-core Systems : A Patterning Approach
- 2015
-
In: 2015 33RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD). - : IEEE. - 9781467371667 ; , s. 573-580
-
Conference paper (peer-reviewed)abstract
- Limitation on power budget in many-core systems leaves a fraction of on-chip resources inactive, referred to as dark silicon. In such systems, an efficient run-time application mapping approach can considerably enhance resource utilization and mitigate the dark silicon phenomenon. In this paper, we propose a dark silicon aware runtime application mapping approach that patterns active cores alongside the inactive cores in order to evenly distribute power density across the chip. This approach leverages dark silicon to balance the temperature of active cores to provide higher power budget and better resource utilization, within a safe peak operating temperature. In contrast with exhaustive search based mapping approach, our agile heuristic approach has a negligible runtime overhead. Our patterning strategy yields a surplus power budget of up to 17% along with an improved throughput of up to 21% in comparison with other state-of-the-art run-time mapping strategies, while the surplus budget is as high as 40% compared to worst case scenarios.
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| 19. |
- Kanth, Rajeev Kumar, et al.
(author)
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Evaluating Sustainability, Environmental Assessment and Toxic Emissions during Manufacturing Process of RFID Based Systems
- 2011
-
In: Dependable, Autonomic and Secure Computing (DASC), 2011 IEEE Ninth International Conference on. - 9781467300063 ; , s. 1066-1071
-
Conference paper (peer-reviewed)abstract
- The present state of the art research in the direction of embedded systems demonstrate that analysis of life-cycle, sustainability and environmental assessment have not been a core focus for researchers. To maximize a researcher's contribution in formulating environmentally friendly products, devising green manufacturing processes and services, there is a strong need to enhance life-cycle awareness and sustainability understandings among embedded systems researchers, so that the next generation of engineers will be able to realize the goal of a sustainable life-cycle. In this work an attempt has been made to investigate and evaluate the life-cycle management and environmental assessment in fabricating processes of the RFID based systems. We have chosen a general life cycle assessment approach which involves the collection and evaluation of quantitative data on the inputs and outputs of materials and energy associated with the RFID based systems. Based on the developed generic models, we have obtained the results in terms of environmental emissions for a production of paper substrate printed RFID antennas. We also make an attempt to raise several sustainability issues and quantify the toxic emissions during the manufacturing process.
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| 20. |
- Kanth, Rajeev Kumar, et al.
(author)
-
Investigation and Evaluation of Life Cycle Assessment of Printed Electronics and its Environmental Impacts Analysis
- 2010
-
Conference paper (peer-reviewed)abstract
- This paper presents cradle to gate life cycle assessment of printed electronics resources. In this work an attempt has been made to investigate and evaluate the life cycle assessment and the environmental impacts of printed electronics resources such as printed RFID antenna. Life cycle inventory analysis for these resources has been carried out to quantify total systems’ inputs and outputs that are relevant to environmental impact especially emissions to air, fresh water. We have also compared printed flexible substrate structure based on polymer substrate with inkjet material deposition to more traditional PCB technology. The chosen approach can be easily relevant to other flexible substrates and materials or device structures.
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| 21. |
- Kanth, Rajeev Kumar, et al.
(author)
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Study on Glass-Epoxy-Based Low-Cost and Compact Tip-Truncated Triangular Printed Antenna
- 2012
-
In: International Journal of Antennas and Propagation. - : Hindawi Publishing Corporation. - 1687-5869 .- 1687-5877. ; , s. 184537-
-
Journal article (peer-reviewed)abstract
- Printed antennas based on glass epoxy substrate have been developed. On the basis of required specifications and assigned frequencies, tip-truncated triangular printed antennas have been designed, analyzed, and fabricated. The performances of the antennas have been measured in terms of return loss, frequency of operation, bandwidth, and radiation pattern. Triangular microstrip antenna (TMSA) configuration consisting of copper as active radiating patch and glass epoxy as dielectric substrate has been screened out to achieve the essential characteristics and satisfying recommended low-cost antenna. The Method of Moment (MOM) analyzing techniques have been employed to realize the required specific properties, whereas optimized tip truncation technique and varying feed point location give rise to suitable LHCP or RHCP configuration of the printed antenna. The coaxial probe signal feed arrangement have been considered for this work. The proposed printed antennas are suitable for communication links between ships or buoys and satellites specially for navigation purpose.
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| 22. |
- Negash, Behailu, et al.
(author)
-
LISA 2.0 : lightweight internet of things service bus architecture using node centric networking
- 2016
-
In: Journal of Ambient Intelligence and Humanized Computing. - : Springer Berlin/Heidelberg. - 1868-5137 .- 1868-5145. ; 7:3, s. 305-319
-
Journal article (peer-reviewed)abstract
- Internet of things (IoT) technologies are advancing rapidly and a wide range of physical networking alternatives, communication standards and platforms are introduced. However, due to differences in system requirements and resource constraints in devices, there exist variations in these technologies, standards, and platforms. Consequently, application silos are formed. In contrast to the freedom of choice attained by a range of options, the heterogeneity of the technologies is a critical interoperability challenge faced by IoT systems. Moreover, IoT is also limited to address new requirements that arise due to the nature of the majority of smart devices. These requirements, such as mobility and intermittent availability, are hardly satisfied by the current IoT technologies following the end-to-end model inherited from the Internet. This paper introduces a lightweight, distributed, and embedded service bus called LISA which follows a Node Centric Networking architecture. LISA is designed to provide interoperability for resource-constrained devices in IoT. It also enables a natural way of embracing the new IoT requirements, such as mobility and intermittent availability, through node centric networking. LISA provides a simple application programming interface for developers, hiding the variations in platform, protocol or physical network, thus facilitating interoperability in IoT systems. LISA is inspired by network on terminal architecture (NoTA), a service centric open architecture originated by Nokia Research Center. Our extensive experimental results show the efficiency and scalability of LISA in providing a lightweight interoperability for IoT systems.
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| 23. |
- Negash, Behailu, et al.
(author)
-
LISA: Lightweight Internet of Things Service Bus Architecture
- 2015
-
In: Procedia Computer Science. - : Elsevier. - 1877-0509. ; 52, s. 436-443
-
Journal article (peer-reviewed)abstract
- A critical challenge faced in Internet of Things (IoT) is the heterogeneous nature of its nodes from the network protocol and platform point of view. To tackle the heterogeneous nature, we introduce a distributed and lightweight service bus, LISA, which fits into network stack of a real-time operating system for constrained nodes in IoT. LISA provides an application programming interface for developers of IoT on tiny devices. It hides platform and protocol variations underneath it, thus facilitating interoperability challenges in IoT implementations. LISA is inspired by the Network on Terminal Architecture (NoTA), a service centric open architecture by Nokia Research Center. Unlike many other interoperability frameworks, LISA is designed specifically for resource constrained nodes and it provides essential features of a service bus for easy service oriented architecture implementation.
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| 24. |
- Nguyen Gia, Tuan, et al.
(author)
-
Fog Computing in Body Sensor Networks : An Energy Efficient Approach
- 2015
-
Conference paper (peer-reviewed)abstract
- Internet of Things based systems provides a viable and organized approach to improve health and wellbeing of mankind. Particularly, health monitoring systems based on wireless body sensor networks become attainable due to increasing number of elderly people that needs healthcare services frequently. In such system, power consumption of a sensor node is an important issue. In order to handle the issue, a smart gateway with fog computing capabilities is presented. Fog computing includes several services such as distributed database management, Electrocardiography (ECG) feature extraction, user graphical interface with access management and push notations. With fog computing, the burden of a cloud server can be reduced and more than 50% of power consumption can be saved at a sensor node. Additionally, through fog computing, the system ensures that the obtained health data can be visualized and diagnosed in real-time even though there is a disconnection between the gateway and cloud server.
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| 25. |
- Noman, Uzair A., et al.
(author)
-
From Threads to Events : Adapting a Lightweight Middleware for Contiki OS
- 2017
-
In: 2017 14TH IEEE ANNUAL CONSUMER COMMUNICATIONS & NETWORKING CONFERENCE (CCNC). - : IEEE. - 9781509061969 ; , s. 486-491
-
Conference paper (peer-reviewed)abstract
- Interoperability is one of the key requirements in the Internet of Things considering the diverse platforms, communication standards and specifications available today. Inherent resource constraints in the majority of IoT devices makes it very difficult to use existing solutions for interoperability, thus demanding new approaches. This paper presents the process of adapting a lightweight interoperability middleware for IoT, LISA, from RIOT to Contiki OS and evaluates memory and power overheads. The middleware follows a service oriented architecture and classifies devices according to available resources to assign different roles, such as Application, Service and Manager Nodes. These roles live in different tiers in a generic IoT architecture, where the Manager nodes are located in the intermediate Fog layer. To adapt to an event based kernel of Contiki, the middleware defines and handles a set of events that are used to communicate with the user application. A network of nodes is simulated to show the architecture promoted by the middleware and the results are presented.
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| 26. |
- Pahikkala, Tapio, et al.
(author)
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A Parallel Online Regularized Least-squares Machine Learning Algorithm for Future Multi-core Processors.
- 2011
-
In: PECCS 2011 - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems 2011. - 9789898425485 ; , s. 590-599
-
Conference paper (peer-reviewed)abstract
- In this paper we introduce a machine learning system based on parallel online regularized least-squares learning algorithm implemented on a network on chip (NoC) hardware architecture. The system is specifically suitable for use in real-time adaptive systems due to the following properties it fulfills. Firstly, the system is able to learn in online fashion, a property required in almost all real-life applications of embedded machine learning systems. Secondly, in order to guarantee real-time response in embedded multi-core computer architectures, the learning system is parallelized and able to operate with a limited amount of computational and memory resources. Thirdly, the system can learn to predict several labels simultaneously which is beneficial, for example, in multi-class and multi-label classification as well as in more general forms of multi-task learning. We evaluate the performance of our algorithm from 1 thread to 4 threads, in a quad-core platform. A Network-on-Chip platform is chosen to implement the algorithm in 16 threads. The NoC consists of a 4×4 mesh. Results show that the system is able to learn with minimal computational requirements, and that the parallelization of the learning process considerably reduces the required processing time.
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| 27. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication
- 2011
-
In: 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011. ; , s. 423-430
-
Conference paper (peer-reviewed)abstract
- In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. Stacked mesh is a feasible architecture which takes advantage of the short inter-layer wiring delays, while suffering from inefficient intermediate buffers. To cope with this, an inter-layer communication mechanism is developed to enhance the buffer utilization, load balancing, and system fault-tolerance. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm for vertical communication. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10, and Negative Exponential Distribution (NED) traffic patterns. In addition, a video conference encoder has been used as a real application for system analysis. Our extensive experiments show significant power and performance improvements compared to a typical stacked mesh 3D NoC.
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| 28. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
BBVC-3D-NoC : An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels
- 2010
-
In: IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 452-453
-
Conference paper (peer-reviewed)abstract
- In this paper, a 3D NoC architecture based on Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate area footprints of vertical interconnects. BBVCs, which can be dynamically self-configured to transmit flits in either direction, enable the system to benefit from a high-speed bidirectional channel instead of a pair of unidirectional channels for inter-layer communication. By exploiting the high-speed nature of the vertical links in 3D ICs, this substitution indicates better bandwidth utilization, lower area footprint, and improved routability at each layer. Our results reveal that the proposed architecture helps to achieve up to 47% savings in TSV area footprint at the 65nm technology node.
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| 29. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures
- 2011
-
In: 5th ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2011. - New York, NY, USA : ACM. ; , s. 65-72
-
Conference paper (peer-reviewed)abstract
- Three-dimensional IC technology offers greater device integration and shorter interlayer interconnects. In order to take advantage of these attributes, 3D stacked mesh architecture was proposed which is a hybrid between packet-switched network and a bus. Stacked mesh is a feasible architecture which provides both performance and area benefits, while suffering from inefficient intermediate buffers. In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called AdaptiveZ for vertical communication. In addition, we hybridize the proposed adaptive routing with available algorithms to mitigate the thermal issues by herding most of the switching activities closer to the heat sink. Our extensive simulations with synthetic and real benchmarks, including the one with an integrated videoconference application, demonstrate significant power, performance, and peak temperature improvements compared to a typical stacked mesh 3D NoC.
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| 30. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Dynamic Power Management for Many-Core Platforms in the Dark Silicon Era : A Multi-Objective Control Approach
- 2015
-
In: Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International Symposium on. - : IEEE conference proceedings. - 9781467380089 ; , s. 219-224
-
Conference paper (peer-reviewed)abstract
- Power management of NoC-based many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates a multi-objective control approach to consider an upper limit on total power consumption, dynamic behaviour of workloads, processing elements utilization, per-core power consumption, and load on network-on-chip. In this paper, we propose a multi-objective dynamic power management method that simultaneously considers all of these parameters. Fine-grained voltage and frequency scaling, including near-threshold operation, and per-core power gating are utilized to optimize the performance. In addition, a disturbance rejecter is designed that proactively scales down activity in running applications when a new application commences execution, to prevent sharp power budget violations. Simulations of dynamic workloads and mixed time-critical application profiles show that our method is effective in honoring the power budget while considerably boosting the system throughput and reducing power budget violation, compared to the state-of-the-art power management policies.
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| 31. |
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| 32. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
LastZ : An Ultra Optimized 3D Networks-on-Chip Architecture
- 2011
-
In: Proceedings - 2011 14th Euromicro Conference on Digital System Design. - 9780769544946 ; , s. 173-180
-
Conference paper (peer-reviewed)abstract
- 3D IC technology enables NoC architectures to offer greater device integration and shorter interlayer interconnects. The primary 3D NoC architectures such as Symmetric 3D Mesh NoC could not exploit the beneficial feature of a negligible inter-layer distance in 3D chips. To cope with this, 3D NoC-Bus Hybrid architecture was proposed which is a hybrid between packet-switched network and a bus. This architecture is feasible providing both performance and area benefits, while still suffering from naive and straightforward hybridization between NoC and bus media. In this paper, an ultra optimized hybridization scheme is proposed to enhance system performance, power consumption, area and thermal issues of 3D NoC-Bus Hybrid Mesh. The scheme benefits from a rule called LastZ which enables ultra optimization of the inter-layer communication architecture. In addition, we present a wrapper to preserve the backward compatibility of the proposed architecture for connecting with the existing network interfaces. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10%, and Negative Exponential Distribution (NED) traffic patterns. Our extensive simulations demonstrate significant area, power, and performance improvements compared to a typical 3D NoC-Bus Hybrid Mesh architecture.
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| 33. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Partial-LastZ : An Optimized Hybridization Technique for 3D NoC Architecture Enabling Adaptive Inter-Layer Communication
- 2012
-
In: International SoC Design Conference. - 9781467329880 ; , s. 281-284
-
Conference paper (peer-reviewed)abstract
- Three-dimensional (3D) integration offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. Stacked mesh 3D NoC architecture was proposed to take advantage of the intrinsic capability of reducing the wire length in 3D ICs. However, this architecture still exacerbates the on-chip power density and router cost. In this paper, we propose a novel hybridization scheme for inter-layer communication using efficient 5-input routers to enhance the overall system power, performance, and area characteristics of the existing Hybrid NoC-Bus 3D mesh architecture. By defining a rule for routing algorithms called LastZ, the proposed area-efficient architecture decreases the overall average hop count of a NoC-based system compared to the existing architectures. We further improve this design by proposing partial-LastZ-based 3D NoC-bus hybrid architecture to provide adaptivity for implementing congestion-aware and fault-tolerant inter-layer routing algorithms. Extensive quantitative experiments demonstrate up to 16% performance improvement compared to the full LastZ-based 3D NoC-bus hybrid architecture and around 20% area reduction compared to the typical hybrid NoC-Bus 3D mesh architecture.
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| 34. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
- 2011
-
In: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011. - Berlin, Heidelberg : Springer Berlin/Heidelberg. - 9783642241536 ; , s. 278-287
-
Conference paper (peer-reviewed)abstract
- 3D NoC offers greater device integration, faster vertical interconnects and more power efficient inter-layer communication due to the beneficial attribute of short through silicon via (TSV) in 3D IC technologies. However, TSV pads used for bonding to a wafer layer, occupy significant chip area and result in routing congestions and expensive manufacturing process. This can lead to a significant reduction in 3D ICs' yield and higher power densities compared to 2D NoCs. In this paper, a power-efficient and low-cost inter-layer communication scheme is proposed as one way to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a high-performance bidirectional channel enables a system to benefit from low-latency nature of the vertical interconnects and to remarkably reduce the number of TSVs. Additionally, we present a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication. Our extensive simulations demonstrate significant area and power improvements compared to a typical symmetric 3D NoC.
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| 35. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs
- 2010
-
In: 7th ACM International Conference on Computing Frontiers, CF'10. - New York, NY, USA : ACM. - 9781450300445 ; , s. 267-276
-
Conference paper (peer-reviewed)abstract
- Distributing a single global clock across a chip while meeting the power requirements of the design is a troublesome task due to shrinking technology nodes associated with high clock frequencies. To deal with this, network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) have been proposed. To interface the islands on a chip, operating at different frequencies, a complex bi-synchronous FIFO design is inevitable. However, these FIFOs are not needed if adjacent switches belong to the same clock domain. In this paper, a Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The FIFO is presented by three different scalable and synthesizable design styles and, in addition, some techniques are suggested to show how the FIFO could be utilized in a VFI-based NoC. Our analysis reveal that the RSBS FIFOs can help to achieve up to 15% savings in the average power consumption of NoC switches and 29% improvement in the total average packet latency in the case of MPEG-4 encoder application, when compared to a non-reconfigurable architecture.
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| 36. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Power-aware NoC router using central forecasting-based dynamic virtual channel allocation
- 2010
-
In: 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. ; , s. 3224-3227
-
Conference paper (peer-reviewed)abstract
- In this paper, we propose a high performance central dynamic virtual channel allocation mechanism for on-chip routers. This central management unit devotes each input port a number of virtual channels (VC) among a shared VC bank based on a traffic forecasting technique. The forecasting technique exploits the link and VC utilizations in predicting the traffic. Based on the predicted traffic, for each input port, the number of active virtual channels may be increased, decreased, or kept unchanged. The clock-gating power management technique is used to activate/deactivate the VCs. Simulation results using uniform and Negative Exponential Distribution (NED) traffic profiles show that a considerable power savings in the virtual channels and overall router power consumption may be achieved especially in low traffic loads. The area overhead of the technique is negligible.
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| 37. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Power-Efficient Inter-Layer Communication Architectures for 3D NoC
- 2011
-
In: 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. - 9780769544472 ; , s. 355-356
-
Conference paper (peer-reviewed)abstract
- In this work, an efficient hybridization architecture to optimize power consumption and system performance of Hybrid NoC-Bus 3D mesh is proposed. Hybrid NoC-Bus 3D mesh is a feasible architecture which takes advantage of the short interlayer wiring delays, while suffering from inefficient intermediate buffers. To address this issue, we propose a mechanism benefiting from a low-power congestion-aware routing algorithm for vertical communication. Our extensive simulations demonstrate significant power and performance improvements compared to a typical Hybrid NoC-Bus 3D architecture.
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| 38. |
- Rahmani, Amir M., et al.
(author)
-
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era
- 2017
-
In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : IEEE Press. - 1063-8210 .- 1557-9999. ; 25:2, s. 427-440
-
Journal article (peer-reviewed)abstract
- Power management of networked many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates considering network characteristics at runtime to achieve better performance while honoring the peak power upper bound. On the other hand, power management has a direct effect on chip temperature, which is the main driver of the aging effects. Therefore, alongside performance fulfillment, the controlling mechanism must also consider the current cores' reliability in its actuator manipulation to enhance the overall system lifetime in the long term. In this paper, we propose a multiobjective dynamic power management technique that uses current power consumption and other network characteristics including the reliability of the cores as the feedback while utilizing fine-grained voltage and frequency scaling and per-core power gating as the actuators. In addition, disturbance rejecter and reliability balancer are designed to help the controller to better smooth power consumption in the short term and reliability in the long term, respectively. Simulations of dynamic workloads and mixed criticality application profiles show that our method not only is effective in honoring the power budget while considerably boosting the system throughput, but also increases the overall system lifetime by minimizing aging effects by means of power consumption balancing.
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| 39. |
- Rahmani, Amir-Mohammad, et al.
(author)
-
Smart e-Health Gateway : Bringing Intelligence to Internet-of-Things Based Ubiquitous Healthcare
- 2015
-
In: 2015 12TH ANNUAL IEEE CONSUMER COMMUNICATIONS AND NETWORKING CONFERENCE. - : IEEE Communications Society. - 9781479963904 ; , s. 826-834
-
Conference paper (peer-reviewed)abstract
- There have been significant advances in the field of Internet of Things (IoT) recently. At the same time there exists an ever-growing demand for ubiquitous healthcare systems to improve human health and well-being. In most of IoT-based patient monitoring systems, especially at smart homes or hospitals, there exists a bridging point (i.e., gateway) between a sensor network and the Internet which often just performs basic functions such as translating between the protocols used in the Internet and sensor networks. These gateways have beneficial knowledge and constructive control over both the sensor network and the data to be transmitted through the Internet. In this paper, we exploit the strategic position of such gateways to offer several higher-level services such as local storage, real-time local data processing, embedded data mining, etc., proposing thus a Smart e-Health Gateway. By taking responsibility for handling some burdens of the sensor network and a remote healthcare center, a Smart e-Health Gateway can cope with many challenges in ubiquitous healthcare systems such as energy efficiency, scalability, and reliability issues. A successful implementation of Smart e-Health Gateways enables massive deployment of ubiquitous health monitoring systems especially in clinical environments. We also present a case study of a Smart e-Health Gateway called UTGATE where some of the discussed higher-level features have been implemented. Our proof-of-concept design demonstrates an IoT-based health monitoring system with enhanced overall system energy efficiency, performance, interoperability, security, and reliability.
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| 40. |
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| 41. |
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| 42. |
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| 43. |
- Tcarenko, Igor, et al.
(author)
-
Smart Energy Efficient Gateway for Internet of Mobile Things
- 2017
-
In: 2017 14TH IEEE ANNUAL CONSUMER COMMUNICATIONS & NETWORKING CONFERENCE (CCNC). - : IEEE. - 9781509061969 ; , s. 1016-1017
-
Conference paper (peer-reviewed)abstract
- Internet of Things (IoT) is a fast developing vision in which physical quantities are digitized, processed and analyzed. Internet of Mobile Things (IoMT) as one of new domains of IoT, due to mobility, requires a more demanding and rigorous solution in many aspects, especially in terms of energy efficiency. We propose a solution consisting of energy efficient and fast hardware platform for building IoMT Fog layer facilities. Experimental results are presented to prove superiority of the proposed hardware in several aspects to popular general purpose platforms.
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| 44. |
- Valinataj, Mojtaba, et al.
(author)
-
A fault-tolerant and hierarchical routing algorithm for NoC architectures
- 2011
-
In: NORCHIP, 2011.
-
Conference paper (peer-reviewed)abstract
- This paper presents a routing method that increases the reliability and product yield of Network-on-Chip (NoC) architectures while incurs a negligible cost. This method has a multi-level fault-tolerance capability and therefore it is capable to tolerate more faulty links and routers with extra cost in higher levels. The proposed algorithm uses dynamic reconfiguration to handle permanent faults but after each configuration it selects new deterministic paths to route the packets. Thus, this algorithm is the reconfigurable extension of deterministic methods. In addition, it is a turn-based routing method and does not need any virtual channel (VC). The effectiveness of the proposed method is evaluated through analysis and simulations. We analytically show that the reliability of a NoC is enhanced by different levels of this method. The experimental results show that the area overhead is only 2.8% for a state of the art router including 64-bit flits and 4-flit input buffers.
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| 45. |
- Valinataj, Mojtaba, et al.
(author)
-
A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip
- 2011
-
In: AEU - International Journal of Electronics and Communications. - : Elsevier BV. - 1434-8411 .- 1618-0399. ; 65:7, s. 630-640
-
Journal article (peer-reviewed)abstract
- High reliability against undesirable effects is one of the key objectives in the design of on-chip networks. This paper presents a very low cost fault-tolerant routing method to tolerate faulty links and routers in mesh-based Networks-on-Chip. This new algorithm can be dynamically reconfigured to support irregular topologies caused by faulty components in a mesh network. In addition, it is a distributed, adaptive and congestion-aware routing algorithm where only two virtual channels are used for both adaptiveness and fault-tolerance. The proposed routing method has a multi-level fault-tolerance capability and therefore it is capable to tolerate more faulty components in more complicated faulty situations with additional hardware costs. The network performance, fault-tolerance capability and hardware overhead are evaluated through appropriate simulations and syntheses. The experimental results show that the overall reliability of a Network-on-Chip is significantly enhanced against multiple component failures with only a small hardware overhead.
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| 46. |
- Yang, Geng, et al.
(author)
-
IoT-Based Remote Pain Monitoring System : From Device to Cloud Platform
- 2018
-
In: IEEE journal of biomedical and health informatics. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-2194 .- 2168-2208. ; 22:6, s. 1711-1719
-
Journal article (peer-reviewed)abstract
- Facial expressions are among behavioral signs of pain that can be employed as an entry point to develop an automatic human pain assessment tool. Such a tool can be an alternative to the self-report method and particularly serve patients who are unable to self-report like patients in the intensive care unit and minors. In this paper, a wearable device with a biosensing facial mask is proposed to monitor pain intensity of a patient by utilizing facial surface electromyogram (sEMG). The wearable device works as a wireless sensor node and is integrated into an Internet of Things (IoT) system for remote pain monitoring. In the sensor node, up to eight channels of sEMG can be each sampled at 1000 Hz, to cover its full frequency range, and transmitted to the cloud server via the gateway in real time. In addition, both low energy consumption and wearing comfort are considered throughout the wearable device design for long-term monitoring. To remotely illustrate real-time pain data to caregivers, a mobile web application is developed for real-time streaming of high-volume sEMG data, digital signal processing, interpreting, and visualization. The cloud platform in the system acts as a bridge between the sensor node and web browser, managing wireless communication between the server and the web application. In summary, this study proposes a scalable IoT system for real-time biopotential monitoring and a wearable solution for automatic pain assessment via facial expressions.
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| 47. |
- Yin, Alexander, et al.
(author)
-
Comparison of Mesh and Honeycomb Network-On-Chip Architectures
- 2012
-
In: Proceedings of the 7th IEEE Conference on Industrial Electronics and Applications. ; , s. 1713-1717
-
Conference paper (peer-reviewed)abstract
- Rectangular Mesh is the most commonly used topology in the field of Network-on-Chip (NoC) due to its high regularity, symmetry and scalability. In this paper, we examine Honeycomb topology as another candidate for NoC architectures. Based on the simulations of Mesh and Honeycomb routers and network, we compare these two topologies in terms of power consumption, area cost and communication delay. Results show that Honeycomb topology outperforms Mesh by at least 25.9%, 54.2% and 30.0% in these three aspects.
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| 48. |
- Yin, Alexander Wei, et al.
(author)
-
Monitoring Agent Based Autonomous Reconfigurable Network-on-Chip
- 2008
-
In: In DAC08 Workshop Digest in Diagnostic Services in Network-on-Chips.
-
Conference paper (peer-reviewed)abstract
- Emerging technologies such as invasive electronics andnano-scale Network-on-Chip systems frequently requireultra-low power and fault tolerance. Implementing thiskind of systems requires the use of a robust monitoringstructure and autonomous self-adjustment. In this paperdifferent distributed system monitoring agentarchitectures are analyzed. The monitored informationcan be used to determine faulty components and to adjustsystem operation points towards minimal energy.
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| 49. |
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