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1.	Illarionov, Yury, et al. (author) Hot-Carrier Degradation and Bias-Temperature Instability in Single-Layer Graphene Field-Effect Transistors : Similarities and Differences 2015 In: IEEE Transactions on Electron Devices. - : IEEE. - 0018-9383 .- 1557-9646. ; 62:11, s. 3876-3881 Journal article (peer-reviewed)abstract We present a detailed analysis of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs) and compare those findings with the bias-temperature instability (BTI). Our results show that the HCD in GFETs is recoverable, similar to its BTI counterpart. Moreover, both the degradation mechanisms strongly interact. Particular attention is paid to the dynamics of HCD recovery, which can be well fitted with the capture/emission time (CET) map model and the universal relaxation function for some stress conditions, quite similar to the BTI in both GFETs and Si technologies. The main result of this paper is an extension of our systematic method for benchmarking new graphene technologies for the case of HCD.
2.	Illarionov, Y., et al. (author) Interplay between hot carrier and bias stress components in single-layer double-gated graphene field-effect transistors 2015 In: European Solid-State Device Research Conference. - : IEEE. - 9781467371339 ; , s. 172-175 Conference paper (peer-reviewed)abstract We examine the interplay between the degradations associated with the bias-temperature instability (BTI) and hot carrier degradation (HCD) in single-layer double-gated graphene field-effect transistors (GFETs). Depending on the polarity of the applied BTI stress, the HCD component acting in conjuction can either accelerate or compensate the degradation. The related phenomena are studied in detail at different temperatures. Our results show that the variations of the charged trap density and carrier mobility induced by both contributions are correlated. Moreover, the electron/hole mobility behaviour agrees with the previously reported attractive/repulsive scattering asymmetry.
3.	Illarionov, Yu.Yu., et al. (author) Bias-temperature instability in single-layer graphene field-effect transistors : A reliability challenge 2014 In: 2014 Silicon Nanoelectronics Workshop, SNW 2014. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479956777 Conference paper (peer-reviewed)abstract We present a detailed analysis of the bias-temperature instability (BTI) of single-layer graphene field-effect transistors (GFETs). We demonstrate that the dynamics can be systematically studied when the degradation is expressed in terms of a Dirac point voltage shift. Under these prerequisites it is possible to understand and benchmark both NBTI and PBTI using models previously developed for Si technologies. In particular, we show that the capture/emission time (CET) map approach can be also applied to GFETs and that recovery in GFETs follows the same universal relaxation trend as their Si counterparts. While the measured defect densities can still be considerably larger than those known from Si technology, the dynamics of BTI are in general comparable, allowing for quantitative benchmarking of the graphene/dielectric interface quality.
4.	Illarionov, Y.Yu., et al. (author) Bias-temperature instability on the back gate of single-layer double-gated graphene field-effect transistors 2016 In: Japanese Journal of Applied Physics. - : Institute of Physics (IOP). - 0021-4922 .- 1347-4065. ; 55:4 Journal article (peer-reviewed)abstract We study the positive and negative bias-temperature instabilities (PBTI and NBTI) on the back gate of single-layer double-gated graphene fieldeffect transistors (GFETs). By analyzing the resulting degradation at different stress times and oxide fields we show that there is a significant asymmetry between PBTI and NBTI with respect to their dependences on these parameters. Finally, we compare the results obtained on the high-k top gate and SiO2 back gate of the same device and show that SiO2 gate is more stable with respect to BTI.
5.	Illarionov, Yu.Yu., et al. (author) Hot-carrier degradation in single-layer double-gated graphene field-effect transistors 2015 In: IEEE International Reliability Physics Symposium Proceedings. - : IEEE conference proceedings. - 9781467373623 ; , s. XT21-XT26 Conference paper (peer-reviewed)abstract We report a first study of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs). Our results show that HCD in GFETs is recoverable, similarly to the bias-temperature instability (BTI). Depending on the top gate bias polarity, the presence of HCD may either accelerate or suppress BTI. Contrary to BTI, which mainly results in a change of the charged trap density in the oxide, HCD also leads to a mobility degradation which strongly correlates with the magnitude of the applied stress.
6.	Illarionov, Yu.Yu., et al. (author) Impact of hot carrier stress on the defect density and mobility in double-gated graphene field-effect transistors 2015 In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. - 9781479969111 ; , s. 81-84 Conference paper (peer-reviewed)abstract We study the impact of hot-carrier degradation (HCD) on the performance of graphene field-effect transistors (GFETs) for different polarities of HC and bias stress. Our results show that the impact of HCD consists in a change of both charged defect density and carrier mobility. At the same time, the mobility degradation agrees with an attractive/repulsive scattering asymmetry and can be understood based on the analysis of the defect density variation.
7.	Kataria, S., et al. (author) Chemical vapor deposited graphene : From synthesis to applications 2014 In: Physica Status Solidi (a) applications and materials science. - : Wiley. - 1862-6300 .- 1862-6319. ; 211:11, s. 2439-2449 Research review (peer-reviewed)abstract Graphene is a material with enormous potential for numerous applications. Therefore, significant efforts are dedicated to large-scale graphene production using a chemical vapor deposition (CVD) technique. In addition, research is directed at developing methods to incorporate graphene in established production technologies and process flows. In this paper, we present a brief review of available CVD methods for graphene synthesis. We also discuss scalable methods to transfer graphene onto desired substrates. Finally, we discuss potential applications that would benefit from a fully scaled, semiconductor technology compatible production process.
8.	Lemme, Max C., et al. (author) Alternative graphene devices : Beyond field effect transistors 2012 In: Device Research Conference (DRC), 2012 70th Annual. - : IEEE. - 9781467311618 ; , s. 24a-24b Conference paper (peer-reviewed)abstract The future manufacturability of graphene devices depends on the availability of large-scale graphene fabrication methods. While chemical vapor deposition and epitaxy from silicon carbide both promise scalability, they are not (yet) fully compatible with silicon technology. Direct growth of graphene on insulating substrates would be a major step, but is still at a very early stage [1]. This has implications on potential entry points of graphene as an add-on to mainstream silicon technology, which will be discussed in the talk.
9.	Lemme, Max C., et al. (author) Graphene for More Moore and More Than Moore applications 2012 In: IEEE Silicon Nanoelectronics Workshop, SNW. - : IEEE. - 9781467309943 ; , s. 6243322- Conference paper (peer-reviewed)abstract Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm 2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment [1, 2] and high contact resistance [3, 4]. In addition, graphene has no energy band gap (Figure 1) and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour [5]. This has steered interest away from logic to analog radio frequency (RF) applications [6, 7]. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology [8]. GFETs slightly lag behind in maximum cut-off frequency F T,max (Figure 2) up to a carrier mobility of 3000 cm 2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves.
10.	Li, Jiantong, et al. (author) A simple route towards high-concentration surfactant-free graphene dispersions 2012 In: Carbon. - : Elsevier BV. - 0008-6223 .- 1873-3891. ; 50:8, s. 3113-3116 Journal article (peer-reviewed)abstract A simple solvent exchange method is introduced to prepare high-concentration and surfactant-free graphene liquid dispersion. Natural graphite flakes are first exfoliated into graphene in dimethylformamide (DMF). DMF is then exchanged by terpineol through distillation, relying on their large difference in boiling points. Graphene can then be concentrated thanks to the volume difference between DMF and terpineol. The concentrated graphene dispersions are used to fabricate transparent conductive thin films, which possess comparable properties to those prepared by more complex methods.
11.	Li, Jiantong, et al. (author) Efficient inkjet printing of graphene 2013 In: Advanced Materials. - : Wiley. - 0935-9648 .- 1521-4095. ; 25:29, s. 3985-3992 Journal article (peer-reviewed)abstract An efficient and mature inkjet printing technology is introduced for mass production of coffee-ring-free patterns of high-quality graphene at high resolution (unmarked scale bars are 100 μm). Typically, several passes of printing and a simple baking allow fabricating a variety of good-performance electronic devices, including transparent conductors, embedded resistors, thin film transistors, and micro-supercapacitors.
12.	Li, Jiantong, et al. (author) Inkjet Printing of MoS2 2014 In: Advanced Functional Materials. - : Wiley-VCH Verlagsgesellschaft. - 1616-301X .- 1616-3028. ; 24:41, s. 6524-6531 Journal article (peer-reviewed)abstract A simple and efficient inkjet printing technology is developed for molybdenum disulfide (MoS2), one of the most attractive two-dimensional layered materials. The technology effectively addresses critical issues associated with normal MoS2 liquid dispersions (such as incompatible rheology, low concentration, and solvent toxicity), and hence can directly and reliably write uniform patterns of high-quality (5-7 nm thick) MoS2 nanosheets at a resolution of tens of micrometers. The technology efficiency facilitates the integration of printed MoS2 patterns with other components (such as electrodes), and hence allows fabricating various functional devices, including thin film transistors, photoluminescence patterns, and photodetectors, in a simple, massive and cost-effective manner while retains the unique properties of MoS2. The technology has great potential in a variety of applications, such as photonics, optoelectronics, sensors, and energy storage.
13.	Lupina, Grzegorz, et al. (author) Residual Metallic Contamination of Transferred Chemical Vapor Deposited Graphene 2015 In: ACS Nano. - : American Chemical Society (ACS). - 1936-0851 .- 1936-086X. ; 9:5, s. 4776-4785 Journal article (peer-reviewed)abstract Integration of graphene with Si microelectronics is very appealing by offering a potentially broad range of new functionalities. New materials to be integrated with the Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etching and electrochemical delamination methods with respect to residual submonolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection X-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10(13) atoms/cm(2). These metal impurities appear to be partially mobile upon thermal treatment, as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics, these results reveal that further progress in synthesis, handling, and cleaning of graphene is required to advance electronic and optoelectronic applications.
14.	Naiini, Maziar M., et al. (author) Embedded Graphene Photodetectors for Silicon Photonics 2014 In: Device Research Conference (DRC), 2014 72nd Annual. - : IEEE conference proceedings. - 9781479954056 ; , s. 43-44 Conference paper (peer-reviewed)abstract Graphene has extraordinary electronic and optoelectronic properties such as high carrier mobility, large charge-carrier concentrations, tunability via electrostatic doping, wavelength-independent absorption, and relatively low dissipation rates [1]. The combination of its electro-optical properties with its manufacturability and CMOS integrability makes graphene an extremely promising candidate for active photonic devices [2,3]. Because of its two-dimensional appearance, graphene has a limited light absorption, which is not enough to fulfill the requirements of silicon photonics technology. Recently, the integration of graphene with silicon waveguides [4,5] has been shown for on-chip applications [6]. In these solutions graphene is placed on top and outside of the waveguide yielding only limited light-graphene interaction. We introduce novel photo-detector architecture by embedding CVD-graphene inside the slot layer of deposited high-k slot waveguides that are compatible with back-end-of-the-line manufacturing of photonic integrated circuits (PICs). This approach leads to a high light-graphene interaction due to the high mode concentration in the slot region[7]. This results in enhanced absorption and enables a very compact photodetector design.
15.	Rodriguez, Saul, et al. (author) A Comprehensive Graphene FET Model for Circuit Design 2014 In: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 61:4, s. 1199-1206 Journal article (peer-reviewed)abstract During the last years, graphene-based field-effect transistors (GFETs) have shown outstanding RF performance; therefore, they have attracted considerable attention from the electronic devices and circuits communities. At the same time, analytical models that predict the electrical characteristics of GFETs have evolved rapidly. These models, however, have a complexity level that can only be handled with the help of a circuit simulator. On the other hand, analog circuit designers require simple models that enable them to carry out fast hand calculations, i.e., to create circuits using small-signal hybrid-pi models, calculate figures of merit, estimate gains, pole-zero positions, and so on. This paper presents a comprehensive GFET model that is simple enough for being used in hand calculations during circuit design and at the same time, it is accurate enough to capture the electrical characteristics of the devices in the operating regions of interest. Closed analytical expressions are provided for the drain current I-D, small-signal transconductance gain g(m), output resistance r(o), and parasitic capacitances C-gs and C-gd. In addition, figures of merit, such as intrinsic voltage gain A(V), transconductance efficiency g(m)/I-D, and transit frequency f(T) are presented. The proposed model has been compared to a complete analytical model and also to measured data available in current literature. The results show that the proposed model follows closely to both the complete analytical model and the measured data; therefore, it can be successfully applied in the design of GFET analog circuits.
16.	Rodriguez, Saul, et al. (author) RF Performance Projections of Graphene FETs vs. Silicon MOSFETs 2012 In: ECS Transactions. - : Electrochemical Society. - 1938-5862 .- 1938-6737. ; 1:5, s. Q39-Q41 Journal article (peer-reviewed)abstract A graphene field-effect-transistor (GFET) model calibrated with extracted device parameters and a commercial 65 nm silicon MOSFET model are compared with respect to their radio frequency behavior. GFETs slightly lag behind CMOS in terms of speed despite their higher mobility. This is counterintuitive, but can be explained by the effect of a strongly nonlinear voltage-dependent gate capacitance. GFETs achieve their maximum performance only for narrow ranges of V-DS and I-DS, which must be carefully considered for circuit design. For our parameter set, GFETs require at least mu = 3000 cm(2) V-1 s(-1) to achieve the same performance as 65 nm silicon MOSFETs.
17.	Rodriguez, Saul, et al. (author) Static Nonlinearity in Graphene Field Effect Transistors 2014 In: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 61:8, s. 3001-3003 Journal article (peer-reviewed)abstract The static linearity performance metrics of the graphene-based field effect transistor (GFET) transconductor are studied and modeled. Closed expressions are proposed for second-and third-order harmonic distortion (HD2, HD3), second-and third-order intermodulation distortion (Delta IM2, Delta IM3), and second-and third-order intercept points (A(IIP2), A(IIP3)). The expressions are validated through large-signal simulations using a GFET VerilogA analytical model and a commercial circuit simulator. The proposed expressions can be used during circuit design to predict the GFET biasing conditions at which linearity requirements are met.
18.	Smith, Anderson D., et al. (author) Biaxial strain in suspended graphene membranes for piezoresistive sensing 2014 In: 2014 IEEE 27th International Conference on Micro Electro Mechanical Systems (MEMS). - : IEEE. - 9781479935093 ; , s. 1055-1058 Conference paper (peer-reviewed)abstract Pressure sensors based on suspended graphene membranes have shown extraordinary sensitivity for uniaxial strains, which originates from graphene's unique electrical and mechanical properties and thinness [1]. This work compares through both theory and experiment the effect of cavity shape and size on the sensitivity of piezoresistive pressure sensors based on suspended graphene membranes. Further, the paper analyzes the effect of both biaxial and uniaxial strain on the membranes. Previous studies examined uniaxial strain through the fabrication of long, rectangular cavities. The present work uses circular cavities of varying sizes in order to obtain data from biaxially strained graphene membranes.
19.	Smith, Anderson David, et al. (author) Graphene-based piezoresistive pressure sensing for uniaxial and biaxial strains 2014 In: 2014 Silicon Nanoelectronics Workshop, SNW 2014. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479956777 Conference paper (peer-reviewed)abstract The piezoresistive effect in graphene has been experimentally demonstrated for both uniaxial and biaxial strains. For uniaxial strain, rectangular membranes were measured while circular membranes provided biaxial strain. Gauge factors have also been extracted and compared to previous literature as well as simulations.
20.	Smith, Anderson D., et al. (author) Large scale integration of graphene transistors for potential applications in the back end of the line 2015 In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 108, s. 61-66 Journal article (peer-reviewed)abstract A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm(2) V-1 s(-1). Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introduting graphene into wafer scale process lines.
21.	Smith, Anderson David, et al. (author) Piezoresistive Properties of Suspended Graphene Membranes under Uniaxial and Biaxial Strain in Nanoelectromechanical Pressure Sensors 2016 In: ACS Nano. - : American Chemical Society (ACS). - 1936-0851 .- 1936-086X. ; 10:11, s. 9879-9886 Journal article (peer-reviewed)abstract Graphene membranes act as highly sensitive transducers in nanoelectromechanical devices due to their ultimate thinness. Previously, the piezoresistive effect has been experimentally verified in graphene using uniaxial strain in graphene. Here, we report experimental and theoretical data on the uni- and biaxial piezoresistive properties of suspended graphene membranes applied to piezoresistive pressure sensors. A detailed model that utilizes a linearized Boltzman transport equation describes accurately the charge-carrier density and mobility in strained graphene and, hence, the gauge factor. The gauge factor is found to be practically independent of the doping concentration and crystallographic orientation of the graphene films. These investigations provide deeper insight into the piezoresistive behavior of graphene membranes.
22.	Smith, Anderson D., et al. (author) Pressure sensors based on suspended graphene membranes 2013 In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 88, s. 89-94 Journal article (peer-reviewed)abstract A novel pressure sensor based on a suspended graphene membrane is proposed. The sensing mechanism is explained based on tight binding calculations of strain-induced changes in the band structure. A CMOS compatible fabrication process is proposed and used to fabricate prototypes. Electrical measurement data demonstrates the feasibility of the approach, which has the advantage of not requiring a separate strain gauge, i.e. the strain gauge is integral part of the pressure sensor membrane. Hence, graphene membrane based pressure sensors can in principle be scaled quite aggressively in size.
23.	Smith, Anderson D., et al. (author) Resistive graphene humidity sensors with rapid and direct electrical readout 2015 In: Nanoscale. - : Royal Society of Chemistry (RSC). - 2040-3364 .- 2040-3372. ; 7:45, s. 19099-19109 Journal article (peer-reviewed)abstract We demonstrate humidity sensing using a change of the electrical resistance of single-layer chemical vapor deposited (CVD) graphene that is placed on top of a SiO2 layer on a Si wafer. To investigate the selectivity of the sensor towards the most common constituents in air, its signal response was characterized individually for water vapor (H2O), nitrogen (N-2), oxygen (O-2), and argon (Ar). In order to assess the humidity sensing effect for a range from 1% relative humidity (RH) to 96% RH, the devices were characterized both in a vacuum chamber and in a humidity chamber at atmospheric pressure. The measured response and recovery times of the graphene humidity sensors are on the order of several hundred milliseconds. Density functional theory simulations are employed to further investigate the sensitivity of the graphene devices towards water vapor. The interaction between the electrostatic dipole moment of the water and the impurity bands in the SiO(2)d substrate leads to electrostatic doping of the graphene layer. The proposed graphene sensor provides rapid response direct electrical readout and is compatible with back end of the line (BEOL) integration on top of CMOS-based integrated circuits.
24.	Smith, Anderson D., et al. (author) Strain engineering in suspended graphene devices for pressure sensor applications 2012 In: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012. - : IEEE. - 9781467301916 ; , s. 21-24 Conference paper (peer-reviewed)abstract The present paper describes a device structure for controlling and measuring strain in graphene membranes. We propose to induce strain by creating a pressure difference between the inside and the outside of a cavity covered with a graphene membrane. The combination of tight-binding calculations and a COMSOL model predicts strain induced band gaps in graphene for certain conditions and provides a guideline for potential device layouts. Raman spectroscopy on fabricated devices indicates the feasibility of this approach. Ultimately, pressure-induced band structure changes could be detected electrically, suggesting an application as ultra-sensitive pressure sensors.
25.	Smith, Anderson, et al. (author) Electromechanical Piezoresistive Sensing in Suspended Graphene Membranes 2013 In: Nano letters (Print). - : American Chemical Society (ACS). - 1530-6984 .- 1530-6992. ; 13:7, s. 3237-3242 Journal article (peer-reviewed)abstract Monolayer graphene exhibits exceptional electronic and mechanical properties, making it a very promising material for nanoelectromechanical devices. Here, we conclusively demonstrate the piezoresistive effect in graphene in a nanoelectromechanical membrane configuration that provides direct electrical readout of pressure to strain transduction. This makes it highly relevant for an important class of nanoelectromechanical system (NEMS) transducers. This demonstration is consistent with our simulations and previously reported gauge factors and simulation values. The membrane in our experiment acts as a strain gauge independent of crystallographic orientation and allows for aggressive size scalability. When compared with conventional pressure sensors, the sensors have orders of magnitude higher sensitivity per unit area.
26.	Smith, Anderson, et al. (author) Wafer Scale Graphene Transfer for Back End of the Line Device Integration 2014 In: INT CONF ULTI INTEGR. - 2330-5738. ; , s. 29-32 Journal article (peer-reviewed)abstract We report on a wafer scale fabrication of graphene based field effect transistors (GFETs) for use in future radio frequency (RF) and sensor applications. The process is also almost entirely CMOS compatible and uses a scalable graphene transfer method that can be incorporated in standard CMOS back end of the line (BEOL) process flows. Such a process can be used to integrate high speed GFET devices and graphene sensors with silicon CMOS circuits.
27.	Vaziri, Sam, et al. (author) A Graphene-Based Hot Electron Transistor 2013 In: Nano letters (Print). - : American Chemical Society (ACS). - 1530-6984 .- 1530-6992. ; 13:4, s. 1435-1439 Journal article (peer-reviewed)abstract We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 10(4).
28.	Vaziri, Sam, et al. (author) A Hysteresis-Free High-k Dielectric and Contact Resistance Considerations for Graphene Field Effect Transistors 2011 In: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. ; 41:7, s. 165-171 Journal article (peer-reviewed)abstract We demonstrate a high-k atomic layer deposition process for graphene field effect transistors which suppresses hysteresis in ambient air measurements. Furthermore, the mobility of the GFETs only degrades by a factor of about two compared to uncovered devices. We further introduce a model that shows the influence of graphene-metal contact resistance at the source and drain on parameter extraction like mobility and transconductance.
29.	Vaziri, Sam, et al. (author) A manufacturable process integration approach for graphene devices 2013 In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 84, s. 185-190 Journal article (peer-reviewed)abstract In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.
30.	Vaziri, Sam, et al. (author) An integration approach for graphene double-gate transistors 2012 In: Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European. - : IEEE. - 9781467317078 ; , s. 250-253 Conference paper (peer-reviewed)abstract In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing and other graphene-based devices.
31.	Vaziri, Sam, et al. (author) Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors 2015 In: Nanoscale. - : Royal Society of Chemistry (RSC). - 2040-3364 .- 2040-3372. ; 7:30, s. 13096-13104 Journal article (peer-reviewed)abstract Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm(-2) (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.
32.	Vaziri, Sam, et al. (author) Going ballistic : Graphene hot electron transistors 2015 In: Solid State Communications. - : Elsevier. - 0038-1098 .- 1879-2766. ; 224, s. 64-75 Journal article (peer-reviewed)abstract This paper reviews the experimental and theoretical state of the art in ballistic hot electron transistors that utilize two-dimensional base contacts made from graphene, i.e. graphene base transistors (GBTs). Early performance predictions that indicated potential for THz operation still hold true today, even with improved models that take non-idealities into account. Experimental results clearly demonstrate the basic functionality, with on/off current switching over several orders of magnitude, but further developments are required to exploit the full potential of the GBT device family. In particular, interfaces between graphene and semiconductors or dielectrics are far from perfect and thus limit experimental device integrity, reliability and performance.
33.	Vaziri, Sam, et al. (author) Graphene base hot electron transistors with high on/off current ratios 2013 In: Dev. Res. Conf. Conf. Dig.. - : IEEE conference proceedings. - 9781479908110 ; , s. 39-40 Conference paper (peer-reviewed)abstract Despite exceptional intrinsic properties of graphene, field effect transistors with graphene channels (GFETs) are limited by the absence of an electronic band gap. The resulting low ION-IOFF ratio and low output resistance makes GFETs unsuitable for logic applications [1] and limits radio frequency (RF) applications [2]. We will present a graphene-based electronic device in which the 0 eV band gap does not limit the device performance: a hot electron transistor (HET) with a graphene base (Graphene Base Transistor, GBT) [3,4]. The single-atomic thinness and high conductivity are decisive advantages of a graphene base [5]. Here, we report on the fabrication and full DC-characterization of GBTs with high ION-IOFF ratio of 105.
34.	Vaziri, Sam, 1978- (author) Graphene Hot-electron Transistors 2016 Doctoral thesis (other academic/artistic)abstract Graphene base transistors (GBTs) have been, recently, proposed to overcome the intrinsic limitations of the graphene field effect transistors (GFETs) and exploit the graphene unique properties in high frequency (HF) applications. These devices utilize single layer graphene as the base material in the vertical hot-electron transistors. In an optimized GBT, the ultimate thinness of the graphene-base and its high conductivity, potentially, enable HF performance up to the THz region. This thesis presents an experimental investigation on the GBTs as well as integration process developments for the fabrication of graphene-based devices.In this work, a full device fabrication and graphene integration process were designed with high CMOS compatibility considerations. To this aim, basic process modules, such as graphene transfer, deposition of materials on graphene, and formation of tunnel barriers, were developed and optimized. A PDMS-supporting graphene transfer process were introduced to facilitate the wet/dry wafer-scale transfer from metal substrate onto an arbitrarily substrate. In addition, dielectric deposition on graphene using atomic layer deposition (ALD) was investigated. These dielectric layers, mainly, served as the base-collector insulators in the fabricated GBTs. Moreover, the integration of silicon (Si) on the graphene surface was studied.Using the developed fabrication process, the first proof of concept devices were demonstrated. These devices utilized 5 nm-thick silicon oxide (SiO2) and about 20 nm-thick aluminum oxide (Al2O3) as the emitter-base insulator (EBI) and base-collector insulator (BCI). The direct current (DC) functionality of these devices exhibited >104 on/off current ratios and a current transfer ratio of about 6%. The performance of these devices was limited by the non-optimized barrier parameters and device manufacturing technology.The possibility to improve and optimize the GBT performance was demonstrated by applying different barrier optimization approaches. Comparing to the proof of concept devices, several orders of magnitude higher injection current density was achieved using a bilayer dielectric tunnel barrier. Utilizing the novel TmSiO/TiO2 (1 nm/6 nm) dielectric stack, this tunnel barrier prevents defect mediated tunneling and, simultaneously, promotes the Fowler-Nordheim tunneling (FNT) and step tunneling (ST). Furthermore, it was shown that Si/graphene Schottky junction can significantly improve the current gain by reducing the electron backscattering at the base-collector barrier. In this thesis, a maximum current transfer ratio of about 35% has been achieved.
35.	Vaziri, Sam, et al. (author) PDMS-supported Graphene Transfer Using Intermediary Polymer Layers 2014 In: PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014). - : IEEE. - 9781479943760 ; , s. 309-312 Conference paper (peer-reviewed)abstract We propose a graphene transfer method based on chemical vapor deposited (CVD) graphene grown on copper foils. This transfer method utilizes a combination of a silicone elastomer (PDMS) and different intermediate polymer layers depending on the process requirements. We use polystyrene and polystyrene/photoresist intermediary layers for dry and wet graphene release. PMMA intermediary layer is applied for bubbling-assisted graphene transfer. The elastomer layer serves as an excellent solid support for electrochemical graphene delamination. Graphene-based field effect transistors (GFETs) were fabricated and characterized using this process. Raman spectroscopy was used in order to verify a successful
36.	Vaziri, Sam, et al. (author) Step tunneling-enhanced hot-electron injection in vertical graphene base transistors 2015 In: European Solid-State Device Research Conference. - : Editions Frontieres. - 9781467371339 ; , s. 198-201 Conference paper (peer-reviewed)abstract This paper presents promising current-voltage characteristics of semiconductor-insulator-graphene tunnel diodes as the hot-electron injection unit in graphene base transistors (GBTs). We propose that by using a bilayer tunnel barrier one can effectively suppress the defect mediated carrier transport while enhancing the hot-electron emission through Fowler-Nordheim tunneling (FNT) and step tunneling (ST). A stack of TmSiO/TiO2 (1 nm/ 5.5 nm) is sandwiched between a highly doped Si substrate and a single layer graphene (SLG) as the electrodes. This tunnel diode exhibits high current with large nonlinearity suitable for the application in GBTs.
37.	Venica, Stefano, et al. (author) Graphene Base Transistors With Bilayer Tunnel Barriers : Performance Evaluation and Design Guidelines 2017 In: IEEE Transactions on Electron Devices. - : IEEE Press. - 0018-9383 .- 1557-9646. ; 64:2, s. 593-598 Journal article (peer-reviewed)abstract Graphene-based capacitors and Graphene base transistors (GBTs) featuring innovative engineered tunnel barriers are characterized in DC and the data are thoroughly analyzed by means of an electrical model and a Monte Carlo transport simulator. Followingmodel calibra-tion on experiments, we then propose strategies to improve the DC common-base current gain and the cutoff frequency of GBTs. The DC and RF performance of optimized GBT structures based on realistic technology data are analyzed in detail to highlight advantages and potential limits of this device concept.
38.	Venica, Stefano, et al. (author) Simulation of DC and RF Performance of the Graphene Base Transistor 2014 In: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 61:7, s. 2570-2576 Journal article (peer-reviewed)abstract We examined the DC and RF performance of the graphene base transistor (GBT) in the ideal limit of unity common base current gain. To this purpose, we developed a model to calculate the current-voltage characteristics of GBTs with semiconductor or metal emitter taking into account space charge effects in the emitter-base and base-collector dielectrics that distort the potential profile and limit the upper value of f(T). Model predictions are compared with available experiments. We show that, in spite of space charge high current effects, optimized GBT designs still hold the promise to achieve intrinsic cutoff frequency in the terahertz region, provided that an appropriate set of dielectric and emitter materials is chosen.
39.	Östling, Mikael, et al. (author) Atomic layer deposition-based interface engineering for high-k/metal gate stacks 2012 In: ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. - : IEEE. - 9781467324724 ; , s. 6467643- Conference paper (peer-reviewed)abstract This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO2), Aluminum-Oxide (Al2O3), Lanthanum-Lutetium-Oxide (LaLuO3) and Lanthanum-Oxide (La 2O3) for CMOS-based device technology are investigated in combination with Silicon (Si) and Germanium (Ge) substrates. Additionally, the use of ALD for deposition of a high-k dielectric gate stack on Graphene is discussed.
40.	Östling, Mikael, et al. (author) Emerging graphene device technologies 2016 In: Emerging Nanomaterials and Devices. - : Electrochemical Society. - 9781607685395 ; , s. 17-35 Conference paper (peer-reviewed)abstract Graphene has a wide range of attractive electrical and mechanical properties. This unique blend of properties make it a good candidate for emerging and future device technologies, such as sensors, high frequency electronics, and energy storage devices. In this review paper, each of the aforementioned applications will be explored along with demonstrations of their operating principles. Specifically, we explore pressure and humidity sensors, graphene base transistor for high frequency applications, and supercapacitors. In addition, this paper provides a general overview of these graphene technologies and, in the case of pressure and humidity sensors, benchmarking against other competing technologies. This paper further shows possible and prospective paths that are suitable for future graphene research to take.

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