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1.	Johnsson, Lennart (author) Performance Modeling of Distributed Memory Architectures 1991 In: Journal of Parallel and Distributed Computing. - 0743-7315 .- 1096-0848. ; 12:4, s. 300-312 Journal article (peer-reviewed)abstract We provide performance models for several primitive operations on data structures distributed over memory units interconnected by a Boolean cube network. In particular, we model single-source and multiple-source concurrent broadcasting or reduction, concurrent gather and scatter operations, shifts along several axes of multidimensional arrays, and emulation of butterfly networks. We also show how the processor configuration, the data aggregation, and the encoding of the address space affect the performance for two important basic computations: the multiplication of arbitrarily shaped matrices and the Fast Fourier Transform. We also give an example of the performance behavior for local matrix operations for a processor with a single path to local memory and a set of processor registers. The analytic models are verified by measurements on the Connection Machine Model CM-2.

Johnsson, Lennart (author)
Performance Modeling of Distributed Memory Architectures
1991
In: Journal of Parallel and Distributed Computing. - 0743-7315 .- 1096-0848. ; 12:4, s. 300-312
Journal article (peer-reviewed)abstract
- We provide performance models for several primitive operations on data structures distributed over memory units interconnected by a Boolean cube network. In particular, we model single-source and multiple-source concurrent broadcasting or reduction, concurrent gather and scatter operations, shifts along several axes of multidimensional arrays, and emulation of butterfly networks. We also show how the processor configuration, the data aggregation, and the encoding of the address space affect the performance for two important basic computations: the multiplication of arbitrarily shaped matrices and the Fast Fourier Transform. We also give an example of the performance behavior for local matrix operations for a processor with a single path to local memory and a set of processor registers. The analytic models are verified by measurements on the Connection Machine Model CM-2.

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