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  • Meraji, Reza, et al. (author)
  • Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
  • 2011
  • In: [Host publication title missing]. - 9781457705144 ; , s. 1-4
  • Conference paper (peer-reviewed)abstract
    • Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology.
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  • Result 1-1 of 1
Type of publication
conference paper (1)
Type of content
peer-reviewed (1)
Author/Editor
Sjöland, Henrik (1)
Öwall, Viktor (1)
Anderson, John B (1)
Meraji, Reza (1)
University
Lund University (1)
Language
English (1)
Research subject (UKÄ/SCB)
Engineering and Technology (1)
Year
2011 (1)

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