| 1. |
- Hu, Jinhong, et al.
(author)
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Safety and immunogenicity of a malaria vaccine, Plasmodium falciparum AMA-1/MSP-1 chimeric protein formulated in montanide ISA 720 in healthy adults
- 2008
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In: PLOS ONE. - : PLOS. - 1932-6203. ; 3:4
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Journal article (peer-reviewed)abstract
- BACKGROUND: The P. falciparum chimeric protein 2.9 (PfCP-2.9) consisting of the sequences of MSP1-19 and AMA-1 (III) is a malaria vaccine candidate that was found to induce inhibitory antibodies in rabbits and monkeys. This was a phase I randomized, single-blind, placebo-controlled, dose-escalation study to evaluate the safety and immunogenicity of the PfCP-2.9 formulated with a novel adjuvant Montanide ISA720. Fifty-two subjects were randomly assigned to 4 dose groups of 10 participants, each receiving the test vaccine of 20, 50, 100, or 200 microg respectively, and 1 placebo group of 12 participants receiving the adjuvant only.METHODS AND FINDINGS: The vaccine formulation was shown to be safe and well-tolerated, and none of the participants withdrew. The total incidence of local adverse events (AEs) was 75%, distributed among 58% of the placebo group and 80% of those vaccinated. Among the vaccinated, 65% had events that were mild and 15% experienced moderate AEs. Almost all systemic adverse reactions observed in this study were graded as mild and required no therapy. The participants receiving the test vaccine developed detectable antibody responses which were boosted by the repeated vaccinations. Sixty percent of the vaccinated participants had high ELISA titers (>1:10,000) of antigen-specific antibodies which could also recognize native parasite proteins in an immunofluorescence assay (IFA).CONCLUSION: This study is the first clinical trial for this candidate and builds on previous investigations supporting PfCP-2.9/ISA720 as a promising blood-stage malaria vaccine. Results demonstrate safety, tolerability (particularly at the lower doses tested) and immunogenicity of the formulation. Further clinical development is ongoing to explore optimizing the dose and schedule of the formulation to decrease reactogenicity without compromising immunogenicity.TRIAL REGISTRATION: Chinese State Food and Drug Administration (SFDA) 2002SL0046; Controlled-Trials.com ISRCTN66850051 [66850051].
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| 2. |
- Hållstedt, Julius, et al.
(author)
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A robust spacer gate process for deca-nanometer high-frequency MOSFETs
- 2006
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:3, s. 434-439
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Journal article (peer-reviewed)abstract
- This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.
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| 3. |
- Qiu, Zhijun, et al.
(author)
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A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering
- 2008
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In: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 55:1, s. 396-403
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Journal article (peer-reviewed)abstract
- An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SUDS is relatively simple in processing, but the silicidation process is dopant-dependent, leading to local variations of silicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation.
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| 4. |
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| 5. |
- Zhang, Zhen, et al.
(author)
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A novel self-aligned process for platinum silicide nanowires
- 2006
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:11-12, s. 2107-2111
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Journal article (peer-reviewed)abstract
- Directly accessible, ultralong, uniform platinum silicide nanowires in PtSi and Pt2Si are mass-fabricated by combining a sidewall transfer lithography (STL) technology and a self-aligned silicide process. The STL technology is based on standard Si technology. The self-aligned platinum silicide (PtSix) process consists of two sequential steps in a single run: a silicidation step in N-2 to ensure a controllable silicide formation followed by an oxidation step in O-2 to form a reliable protective SiOx layer on top of the grown PtSix. The achieved nanowires are characterised by a low resistivity: 26 +/- 3 and 34 +/- 2 mu Omega cm for the Pt2Si- and PtSi-dominated nanowires.
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| 6. |
- Zhang, Zhen, 1979-
(author)
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Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
- 2008
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Doctoral thesis (other academic/artistic)abstract
- The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices. First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts. Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp). Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM. Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap.
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| 7. |
- Zhang, Zhen, et al.
(author)
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Ni2Si nanowires of extraordinarily low resistivity
- 2006
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In: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 88:21, s. 213103-
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Journal article (peer-reviewed)abstract
- Ultralong, polycrystalline Ni2Si nanowires are fabricated by combining sidewall transfer lithography with self-aligned silicidation. Upon formation at 500 degrees C, the nanowires that are 400 mu m long with a rectangular cross section of 37.5 by 25.3 nm are characterized by a resistivity of 25 +/- 1 mu Omega cm which is similar to the value for Ni2Si thin films. Further annealing at 800 degrees C results in an extraordinarily low wire resistivity of 10 mu Omega cm. Such a drastic decrease in resistivity is attributed to a significant grain growth and a low density of defects in the nanowires.
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| 8. |
- Zhang, Zhen, et al.
(author)
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Performance fluctuation of FinFETs with Schottky barrier source/drain
- 2008
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In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 29:5, s. 506-508
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Journal article (peer-reviewed)abstract
- A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.
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| 9. |
- Zhang, Zhen, et al.
(author)
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Robust, scalable self-aligned platinum silicide process
- 2006
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In: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 88:14, s. 142114-
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Journal article (peer-reviewed)abstract
- A robust, scalable PtSix process is developed. The process consists of two consecutive annealing steps in a single run; the first is silicidation of Pt films on Si substrates carried out in N-2, whereas the second is surface oxidation of the resultant PtSix in O-2. By adequately adjusting the temperature during the oxidation step, a protective SiOx hard mask forms on PtSix of different thicknesses and compositions. Such a surface oxidation is absent for Pt on SiO2 isolation, which is crucial for the subsequent selective wet etch for a self-aligned process. Ultralong PtSix nanowires are fabricated using this robust self-aligned process.
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| 10. |
- Zhang, Zhen, et al.
(author)
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SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation
- 2008
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In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 29:1, s. 125-127
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Journal article (peer-reviewed)abstract
- MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.
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