| 1. |
- Strak, Adam, et al.
(author)
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Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits
- 2008
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In: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268 .- 1549-8328 .- 1558-0806. ; 55:4, s. 1041-1054
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Journal article (peer-reviewed)abstract
- This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.
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| 2. |
- Garrido, Mario, 1981-, et al.
(author)
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A Pipelined FFT Architecture for Real-Valued Signals
- 2009
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In: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 56:12, s. 2634-2643
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Journal article (peer-reviewed)abstract
- This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fast Fourier trans-form (RFFT). The proposed architecture takes advantage of the re-duced number of operations of the RFFT with respect to the com-plex fast Fourier transform (CFFT), and requires less area whileachieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computa-tion of the RFFT, which, contrary to previous approaches, presentsa regular geometry suitable for the implementation of hardwarestructures. Moreover, the algorithm can be used for both the deci-mation in time (DIT) and decimation in frequency (DIF) decompo-sitions of the RFFT and requires the lowest number of operationsreported for radix 2.Finally, as in previous works, when calculating the RFFT theoutput samples are obtained in a scrambled order. The problemof reordering these samples is solved in this paper and a pipelinedcircuit that performs this reordering is proposed.
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| 3. |
- Kozmin, Kirill, et al.
(author)
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Level-crossing ADC performance evaluation toward ultrasound application
- 2009
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In: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 56:8, s. 1708-1719
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Journal article (peer-reviewed)abstract
- A performance evaluation of a level-crossing analog-to-digital converter (ADC) is presented. It is shown that its signal-to-noise ratio (SNR) does not depend on the input-signal amplitude, which results in an almost-flat SNR for amplitudes that fall into the Nyquist criteria for irregular sampling. The influence of the reconstruction procedure on SNR is discussed, and possible limitations due to the comparator and clock on the performance of the ADC are analyzed. This analysis allows for specification of comparator and clock parameters such that they do not limit the ADC performance yet are not overestimated. In conclusion, a previously known level-crossing ADC design procedure is extended.
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| 4. |
- Sköldberg, Jonas, 1971, et al.
(author)
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Nanocell Devices and Architecture for Configurable Computing With Molecular Electronics
- 2007
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In: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 54:11, s. 2461-
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Journal article (peer-reviewed)abstract
- We develop a method to configure a 3-D nonlinearnanoparticle-molecule network to performing ten out of twelvepossible combinations of two 2-bit logic gates with shared inputs.The logic gates are based on a simple circuit with adjustablelinear and fixed negative differential resistance (NDR) elements.A bistable latch for signal restoration is an integral part of thistarget circuit. The simulations show that conductive patternscan be formed by applying voltages on the input–output pinsof the nanocell. They also show that one-link gaps (short highlyresistive links) can be created within the conductive channels.Furthermore, we discuss methods for introducing NDR moleculesin these gaps, a crucial element of the target circuit. The structuresresulting from the simulations are put in an architectural context,in which complex functions can be realized from the individualnanocell logic gates.
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| 5. |
- Alty, S. R., et al.
(author)
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Efficient time-recursive implementation of matched filterbank spectral estimators
- 2005
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In: IEEE Transactions on Circuits And Systems Part I. - 1057-7122 .- 1558-1268. ; 52:3, s. 516-521
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Journal article (peer-reviewed)abstract
- In this paper, we present a computationally efficient sliding window time updating of the Capon and amplitude and phase,estimation (APES) matched filterbank spectral estimators based on the time-variant displacement structure of the data covariance matrix. The presented algorithm forms a natural extension of the most computationally efficient algorithm to date, and offers a significant computational gain as compared to the computational complexity associated with the batch re-evaluation of the spectral estimates for each time-update. Furthermore, via simulations, the algorithm is found to be numerically superior to the time-updated spectral estimate formed from directly updating the data covariance matrix.
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| 6. |
- Andersson, Ola, et al.
(author)
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Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters
- 2005
-
In: IEEE Transactions on Circuits and Systems I: Regular Papers. - Piscataway : IEEE. - 1549-8328. ; 52:11, s. 2265-2275
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Journal article (peer-reviewed)abstract
- The current-steering digital-to-analog converter (DAC) is the most common type of DAC for high-speed applications. Glitches present in the DAC output contribute to nonlinear distortion in the DAC transfer characteristics degrading the circuit performance. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A behavioral-level model of this nonideal behavior is derived in this work. Further, a method with low computational complexity for estimating the influence of the modeled errors in the frequency domain is developed. This method can be utilized by circuit designers to derive circuit requirements for fulfilling a given frequency-domain specification, potentially relaxing the requirements compared with a worst-case analysis. Examples of model utilization are given in terms of an analytical examination and MATLAB simulations. A good agreement between simulated and analytical results is obtained.
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| 7. |
- Andreani, Pietro
(author)
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A time-variant analysis of the 1/f2 phase noise in CMOS parallel LC-tank quadrature oscillators
- 2006
-
In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 53:8, s. 1749-1760
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Journal article (peer-reviewed)abstract
- This paper presents a study of 1/f/sup 2/ phase noise in quadrature oscillators built by connecting two differential LC-tank oscillators in a parallel fashion. The analysis clearly demonstrates the necessity of adopting a time-variant theory of phase noise, where a more simplistic, time-invariant approach fails to explain numerical simulation results even at the qualitative level. Two topologies of 5-GHz parallel quadrature oscillators are considered, and compact but nevertheless highly general, closed-form formulas are derived for the phase noise caused by the losses in the LC-tanks and by the noisy currents in the MOS transistors. A large number of spectreRF simulations, covering a wide range of working conditions for the oscillators, is used to validate the theoretical analysis.
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| 8. |
- Hedberg, Hugo, et al.
(author)
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Low-Complexity Binary Morphology Architectures with Flat Rectangular Structure Elements
- 2008
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In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 55:8, s. 2216-2225
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Journal article (peer-reviewed)abstract
- This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing applications. Hence, the aim is to minimize the number of operations, memory requirement, and memory accesses per pixel. The main advantage of the proposed architecture is that for the common class of flat and rectangular SEs, complexity and number of memory accesses per pixel is low and independent of both image and SE size. The proposed design is compared to the more common delay-line architecture in terms of complexity, memory requirements and execution time, both for an actual implementation and as a function of image resolution and SE size. The architecture is implemented for the UMC 0.13- $mu{hbox {m}}$ CMOS process using a resolution of 640 $times$ 480. A maximum SE of 63 $times$ 63 is supported at an estimated clock frequency of 333 MHz.
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| 9. |
- Jalali-Farahani, Bahar, et al.
(author)
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Adaptive noise cancellation techniques in sigma-delta analog-to-digital converters
- 2007
-
In: Ieee Transactions on Circuits and Systems I-Regular Papers. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1057-7122. ; 54:9, s. 1891-1899
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Journal article (peer-reviewed)abstract
- Adaptive noise cancellation (ANC)) techniques that extract a desired signal from background noise have many applications in different engineering disciplines. In ANC, the corrupted signal is passed through a filter that tends to suppress the noise while leaving the original signal unchanged. This paper demonstrates that the adaptive noise cancellation technique can be embedded in the digital signal postprocessing of a sigma-delta analog-to-digital converter and effectively reduces the quantization noise as well as the thermal noise at the output of the converter. The combination of ANC and the noise-shaping technique enable high-resolution analog-to-digital conversion in wideband applications where noise shaping alone cannot provide enough suppression of quantization noise due to the low oversampling ratio.
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| 10. |
- Kamuf, Matthias, et al.
(author)
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Optimization and implementation of a Viterbi decoder under flexibility constraints
- 2008
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In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 55:8, s. 2411-2422
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Journal article (peer-reviewed)abstract
- This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13- $mu{hbox {m}}$ CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.
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