| 1. |
- Abbas, Muhammad, et al.
(author)
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On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure
- 2013
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In: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:4, s. 926-937
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Journal article (peer-reviewed)abstract
- In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.
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| 2. |
- Buonomo, Antonio, et al.
(author)
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A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation
- 2013
-
In: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:12, s. 3126-3135
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Journal article (peer-reviewed)abstract
- This paper proposes a simple and effective modification of the conventional divide-by-two injection locked frequency divider (ILFD) with direct-injection aimed at allowing both the divide-by-two and the divide-by-three modes of operation. The proposed circuit does not employ additional inductors as usual in divide-by-three ILFDs, but exploits the combined effect of two independent injection techniques. The resulting locking range for the divide-by-three mode is comparable in size to that for the divide-by-two. Thus, the proposed circuit can be an optimum alternative to existing dividers, due to the flexibility of two division ratios and due to the absence of additional inductors. An intuitive explanation of the locking mechanism underlying this ILFD and a quantitative analysis are provided, allowing one to predict the amplitude and phase of oscillation in the locked mode, as well as the locking range, with approximate closed-form expressions. Measurements on a circuit prototype and results from SPICE simulations demonstrate the effectiveness of the circuit and validate the theoretical model and the resulting formulas.
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| 3. |
- Chen, Sau-Gee, et al.
(author)
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Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
- 2014
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In: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:10, s. 2869-2877
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Journal article (peer-reviewed)abstract
- This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
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| 4. |
- Fazli Yeknami, Ali, et al.
(author)
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Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
- 2014
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In: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 61:2, s. 358-370
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Journal article (peer-reviewed)abstract
- A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.
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| 5. |
- Garrido Gálvez, Mario, et al.
(author)
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Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI)
- 2014
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In: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:7, s. 2002-2012
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Journal article (peer-reviewed)abstract
- This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, the shift-and-add implementation uses advanced single constant multiplication (SCM) and multiple constant multiplication (MCM) techniques that lead to low-complexity multiplierless implementations. Third, the design of the rotators is done by a joint optimization of the coefficient selection and shift-and-add implementation. As a result, the CCSSI provides an extended design space that offers a larger number of alternatives with respect to previous works. Furthermore, the design space is explored in a simple and efficient way. The proposed approach has wide applications in numerous hardware scenarios. This includes rotations by single or multiple angles, rotators in single or multiple branches, and different scaling of the outputs. Experimental results for various scenarios are provided. In all of them, the proposed approach achieves significant improvements with respect to state of the art.
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| 6. |
- Gustavsson, Ulf, 1975, et al.
(author)
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An RF Carrier Bursting System using Partial Quantization Noise Cancellation
- 2012
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In: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 59:3, s. 515-528
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Journal article (peer-reviewed)abstract
- This paper introduces a novel method for bandpass cancellation of the quantization noise occurring in high efficiency, envelope pulsed transmitter architectures - or carrier bursting. An equivalent complex baseband model of the proposed system, including the Sigma Delta-modulator and cancellation signal generation, is developed. Analysis of the baseband model is performed, leading to analytical expressions of the power amplifier drain efficiency, assuming the use of an ideal class B power amplifier. These expressions are further used to study the impact of key system parameters, i.e. the compensation signal variance and clipping probability, on the class~B power amplifier drain efficiency and signal-to-noise ratio.The paper concludes with simulations followed by practical measurements in order to validate the functionality of the method and to evaluate the performance-trend predictions made by the theoretical framework in terms of efficiency and spectral purity.
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| 7. |
- Gustavsson, Ulf, 1975, et al.
(author)
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Quantization Noise Minimization in ΣΔ-modulation based RF Transmitter Architectures
- 2010
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In: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 57:12, s. 3082-3091
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Journal article (peer-reviewed)abstract
- In this paper we describe an optimization method for minimization of quantization noise in ΣΔ-based RF transmitters. The aim of the method is to enable the use of reconstruction filters with wider passband, or alternatively, a lower switch-rate. The method uses a general representation of the ΣΔ-converters in combination with a differentiable approximation of the quantizer. Based on this, a Monte-Carlo based algorithm is developed around the damped Gauss-Newton iteration. As a result of the suggested algorithm, the residual quantization noise after reconstruction filtering is significantly decreased. Finally, simulations using a bandlimited signal with a Gaussian distribution are used to demonstrate the capabilities of the suggested algorithm when applied with the proposed ΣΔ-modulator representation. The resulting performance is compared to several cases of traditional integrator based ΣΔ-converters, demonstrating significant improvements in terms of reduced reconstruction normalized mean square error (NMSE). This implicates that the transmitter efficiency can be improved with minor changes in the modulator implementation.
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| 8. |
- Hoang, Tung, 1980, et al.
(author)
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A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit
- 2010
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In: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 57:12, s. 3073-3081
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Journal article (peer-reviewed)abstract
- We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial-product generation circuitry and a reduction tree, while the second stage, thanks to a special sign-extension solution, implements all other functionality. Place-and-route evaluations using a 65-nm 1.1-V cell library show that the proposed architecture offers a 31% improvement in speed and a 32% reduction in energy per operation, averaged across operand sizes of 16, 32, 48, and 64 bits, over a reference two-cycle MAC architecture that employs a multiplier in the first stage and an accumulator in the second. When operating the proposed architecture at the lower frequency of the reference architecture the available timing slack can be used to downsize gates, resulting in a 52% reduction in energy compared to the reference. We extend the new architecture to create a versatile double-throughput MAC (DTMAC) unit that efficiently performs either multiply-accumulate or multiply operations for N-bit, 1 × N/2-bit, or 2 × N/2-bit operands. In comparison to a fixed-function 32-bit MAC unit, 16-bit multiply-accumulate operations can be executed with 67% higher energy efficiency on a 32-bit DTMAC unit. © 2006 IEEE.
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| 9. |
- Jakobsson, Anders, et al.
(author)
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Frequency Synthesizer With Dual Loop Frequency and Gain Calibration
- 2013
-
In: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 60:11, s. 2911-2919
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Journal article (peer-reviewed)abstract
- A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 $mu$ m CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain ($K_{rm VCO}$ of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump current and loop filter capacitance to an accuracy of 5%. The PLL settles in 150 $mu$s including frequency and gain calibrations. No switches are used in the loop filter. The output phase noise at 1-MHz offset is ${-}123$ dBc/Hz and the integrated phase error (1 kHz–2 MHz) is 1.26 $^{circ}$.
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| 10. |
- Jing Xu, Wei, et al.
(author)
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Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters
- 2014
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In: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:3, s. 764-777
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Journal article (peer-reviewed)abstract
- The paper proposes an optimization technique for the design of variable digital filters with simultaneously tunable bandedge and fractional delay using a fast filter bank (FFB) approach. In the FFB approach, full band signals are split into multibands, and each band is multiplied by a proper phase shift to realize the variable fractional delay. In the proposed technique, in the formulation of the optimization of the 0th stage prototype filter of the FFB, the ripples of the filters in the subsequent stages are all taken into consideration. In addition, a shaping filter is applied to the last retained band of the FFB to form the transition band of the variable filter, such that the transition width of each band in the FFB can be relaxed to reduce the computational complexity. In total three shaping filters, constructed from a prototype filter, can be shared by different bands, so that the extra cost incurred due to the shaping filter is low.
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