| 1. |
- Mishukova, Viktoriia
(author)
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Direct patterning processes for high-performance microsupercapacitors
- 2023
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Doctoral thesis (other academic/artistic)abstract
- The surge in miniaturized electronic components driven by the Internet of Things (IoT) has prompted an interest in non-traditional energy storage solutions. For these applications, reduction of size while preserving power and energy densities are of great importance. Within this context, planar microsupercapacitors (MSCs) have emerged as strong candidates for energy storage. Their unique two-dimensional structure, rapid charge-discharge capabilities, high power density, and enduring stability make them highly appealing as power units for on-chip integration.However, the intricate nature of MSC fabrication remains a substantial challenge. Conventionally used indirect patterning processes, such as photolithography, are limiting the implementation of novel functional nanomaterials with high charge storing capacities. As a result, other kinds of direct patterning processes can be used to fabricate state-of-the-art MSCs. Recent studies mainly focused on improving the patterning geometry, minimizing electrode dimensions and narrowing the electrode gap to maintain high resolution of MSCs. However, these efforts were made at the expense of process scalability potential and degree of complexity of the fabrication processes. This thesis aims to develop fabrication process flows with emphasis on simplicity and versatility without sacrificing the possibility for large-scale fabrication of MSCs with high-performance.The first part of this thesis describes the implementation of highly scalable inkjet printing process for fabrication of high-performance MSCs. Typically, inkjet printing can be used to deposit thin films of materials. However, to fabricate MSCs with high-performance, the thickness is a crucial parameter that requires scaling up. The contribution of the first work is dealing with overcoming printing limitations by describing a step-like fabrication process that was developed to overcome the limitations of inkjet printing to increase the thickness of the electrode material, and, therefore its electrochemical performance. The outcome graphene-based solid-state MSCs free from metallic current collector exhibit high areal capacitance of 0.1mF cm−2 and hold promise for on-chip fabrication. In the second work, a facile integration of inkjet printing with an electrodeposition technique is used to fabricate hybrid flexible MSCs based on graphene, Fe2O3, and MnO2 nanomaterials with∼90% capacitance retention after 10 000 charge-discharge cycles.In the second part of this thesis, direct laser writing process is implemented as a viable alternative to fabrication of planar MSCs, based on a variety of highly electrochemically active nanomaterials that are not compatible with inkjet printing. In the third, fourth, and fifth works binder-free ink formulation approaches were developed to fabricate composite nanomaterial films based on graphene, graphene oxide, carbon nanotubes (CNTs), and polyaniline (PANI). Efficient patterning of these films, thanks to the wide range of controls over the laser beam, was realized highlighting the simplicity of the developed fabrication processes for MSCs with high areal capacitance of 172 mF cm−2. Furthermore, it enabled the fabrication of MSCs that can operate in a wide temperature range from 25 to 250 °C.In summary, this thesis reshapes the MSC fabrication process by considering performance, scalability, and process adaptability towards novel functional nanomaterials. These proposed methods are further strengthened by innovative ink formulation strategies using these materials, highlighting their potential applicability in emergent energy storage devices.
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| 2. |
- Xue, Han
(author)
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Functional Materials for Sustainable Energy Harvesting and Energy Storage Devices
- 2024
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Doctoral thesis (other academic/artistic)abstract
- The booming evolution of portable, wearable electronic devices, wireless sensors, and integrated microelectronics has stimulated the need for miniaturized power supply modules. Energy harvesters, which harness the environmental energy for electricity use, and micro super capacitors (MSCs),known for the small form factor and rapid power delivery, provide energy efficient solutions. Meanwhile, the demand for sustainable development hasdriven the research towards environmental and ecological-friendly energy solutions. In light of this, utilizing paper as a substrate offers a promising avenue due to its sustainability, lightweight nature, disposability, and availability. Integrating energy harvesters and micro super capacitors into on paper micro-power sources holds the potential for ready-to-use smartelectronics, such as biosensors for detection and diagnostics.Nonetheless, the progress of on-paper MSCs is still in its infancy encountering challenges in appropriate material selection, structure, and fabrication design. 2D material MXene and conducting polymer PEDOT:PSS hold promises for on-paper MSCs thanks to their hydrophilic nature and excellent electrochemical properties. In terms of energy harvesting units,hydrovoltaic technologies that generate electricity from water movement offer a sustainable energy solution, while triboelectric nanogenerators (TENGs) harness the ubiquitous mechanical energy in the environment to produce electrical power. Such electric energy can be directly utilized or stored with the assistance of MSCs for later consumption. However, integrating energy harvesting and storage components on paper involves complex material and fabrication requirements. This thesis aims at enhancing the rate capability (thecharge and discharge ability at high rates while maintaining the storage capacity) of on-paper MSCs, advancing the development of hydrovoltaic and TENGs energy harvesters and eventually integrating TENGs and MSCs to a non-paper power supply.The first part (Paper I and Paper II) of this thesis presents the improvements in the rate performance (the ability to maintain the efficiency and capacityunder different rates) of the on-paper MSCs. Introducing conducting polymerpoly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) to othermaterials is a typical approach to improve the conductivity of coatings/patternson paper. However, due to the cancel-out effect caused by opposite carrier typesof PEDOT:PSS and Ti3C2Tx, the blend of both showcases a lowered electrical conductivity, thus degrading rate performance. In the first study, a heterogeneous structure design was proposed to tackle this issue. The high efficiency and through put of direct ink writing, along with the minimal damageon the paper substrate of fem to second laser scribing technologies, enable effective MSC fabrication on paper, resulting in stacked-structure MSCs that exhibit excellent areal capacitance of 5.7 mF/cm2 at a high scan rate of 1000mV/s without metallic current collectors. In the second study, the rateperformance was further improved by mixing another type of MXene, Ti2CTx,with PEDOT:PSS which share the same carrier type, avoiding the complex structure and facilitating the printing process. The composite exhibits increased conductivity and an areal capacitance of 30.2 mF/cm2, over fivefold higher than the PEDOT/ Ti3C2Tx heterogeneous structure. The composite ink also enables the efficient fabrication of MSC arrays on paper, which can be charged and discharged at an ultrahigh scan rate of 10 V/s and can work at an extended stable voltage window of 6 V, indicating the excellent scalability of thePEDOT:PSS-Ti2C composite-based electrode.The second part (Paper III and Paper IV) of this thesis focuses on the development of energy harvesters. Current monolayer graphene-based hydrovoltaic energy harvesters face challenges in fabrication complexity and low output power. To eliminate these limitations, a hydrovoltaic energyharvester based on the composite films of electrochemically exfoliated graphene and TiO2 nanoparticles was developed through a simple doctor blading method. The device delivers a peak voltage of 75 mV and a maximized output power of 1.8 μW at low waving velocities. Besides, tribo electric nanogenerators (TENGs) which convert mechanical movements to electric energy can produce higher instantaneous voltage and can be developed on paper with printing techniques. Thus, the on-paper spacer-free TENGs withgood working stability and improved compactness were fabricated. Moreover, by employing PEDOT:PSS as both electrodes in TENGs and MSCs, TENGs and MSCs can be directly printed on paper, and integrated with a small chip rectifier, achieving the fully printed on-paper micro-power supply. In this preliminary integrated system, the mechanical energy is continuously harvested and converted to electric energy by a TENG, and simultaneously stored in the MSC array, showing the potential to power paper electronics.In conclusion, this thesis unveils the development of sustainable on-papermicrosupercapacitors with outstanding rate performance and two energyharvesters that convert renewable energy into electricity. In the end, the thesis finalizes with a primary integration of harvesting and storage parts into an on paper power supply.
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| 3. |
- Zurauskaite, Laura
(author)
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Ge/high-k Gates for Monolithic 3D Integration
- 2021
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Doctoral thesis (other academic/artistic)abstract
- Continuous scaling of transistor dimensions has been in the heart of semiconductorindustry for many years. Recently the scaling has been enabled by various performance boosters which resulted in increased processing complexity and cost, forcing the chip manufacturers to look for some alternative solutions. Monolithic 3D integration has been identified as a promising candidate for future CMOS technology nodes, as it could enable a further increasein device density through stacking tiers of older and cheaper generation transistorson top of each other. One of the major challenges faced by monolithic 3D integration is the thermal budget during upper tier fabrication since high temperature steps used in conventional CMOS processing can damage the bottom tier devices. To this respect, Ge has an advantage over Si due to its intrinsically low processing temperature. However, realizing Ge devices that provide performance and reliability comparable to Si devices is not straight forward. Gate stack formation in Ge devices is particularly challenging, as Ge lacks a stable oxide for surface passivation.In this work, gate stack solutions for Ge-based devices for monolithic 3D integration applications have been extensively studied. Low temperature Ge surface passivation with GeOx and Si-cap process has been investigated and characterized in terms of interface state density, oxide trap density and fixed charge density. GeOx has been integrated with other high-k dielectrics, suchas Al2O3, Tm2O3 and HfO2, and with the help of post deposition and forming gas treatments provided sufficient surface passivation with low interface state density. However, devices with GeOx passivation suffered from poor reliability stemming from the lack of thermal stability and high oxide trap density in GeOx layer. On the other hand, Si-cap integrated with TmSiO interfacial layer has been shown to provide both low interface trap density and oxide trap density, albeit within a narrow process window for Si-cap growth conditions. Selected gate stacks with GeOx and Si-cap passivation have been integrated in Ge pFET process on in-house fabricated germanium on insulator substrates. Subthreshold slope values inline with previous reports have been achieved, as well as 60 % higher hole mobility than in reference silicon on insulator pFETs. Moreover, initial results of Si-cap and TmSiO interfacial layer integration ingermanium on insulator nFETs have been demonstrated.This work presents both advantages and limitations of each gate stacksolution on Ge platform. The processes employed in this work are monolithic 3D integration compatible, and demonstrate that with some process optimization Ge transistors could be integrated on Si platform in monolithic3D integration fashion.
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| 4. |
- Abedin, Ahmad, 1984-
(author)
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Germanium layer transfer and device fabrication for monolithic 3D integration
- 2021
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Doctoral thesis (other academic/artistic)abstract
- Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. On the one hand, the scaling of devices isreaching critical dimensions, which makes their further downscaling techno-logically difficult and economically challenging, whereas, on the other hand,the field of electronics is no longer limited only to developing circuits thatare meant for data processing. Sensors, processors, actuators, memories, andeven power storage units need to be efficiently integrated into a single chip tomake IoT work. M3D integration through stacking different layers of deviceson each other can potentially improve circuits’ performance by shorteningthe wiring length and reducing the interconnect delay. Using multiple tiersfor device fabrication makes it possible to integrate different materials withsuperior physical properties. It offers the advantage of fabricating higher-performance devices with multiple functionalities on a single chip. However,high-quality layer transfer and processing temperature budget are the majorchallenges in M3D integration. This thesis involves an in-depth explorationof the application of germanium (Ge) in monolithic 3D integration.Ge has been recognized as one of the most promising materials that canreplace silicon (Si) as the channel material for p-type field-effect transistors(pFETs) because of its high hole mobility. Ge pFETs can be fabricated atsubstantially lower temperatures compared to Si devices which makes theformer a good candidate for M3D integration. However, the fabrication ofhigh-quality Ge-on-insulator (GOI) layers with superior thickness homogene-ity, low residual doping, and a sufficiently good interface with buried oxide(BOX) has been challenging.This thesis used low-temperature wafer bonding and etch-back techniquesto fabricate the GOI substrate for M3D applications. For this purpose, aunique stack of epitaxial layers was designed and fabricated. The layer stackcontains a Ge strain relaxed buffer (SRB) layer, a SiGe layer to be used asan etch stop, and a top Ge layer to be transferred to the handling wafer.The wafers were bonded at room temperature, and the sacrificial wafer wasremoved through multiple etching steps leaving 20 nm Ge on the insulatorwith excellent thickness homogeneity over the wafer. Ge pFET devices werefabricated on the GOI substrates and electrically characterized to evaluatethe layer quality. Finally, the epitaxial growth of the highly doped SiGeand sub-nm Si cap layers have been investigated as alternatives for improvedperformance Ge pFETs.The Ge buffer layer was developed through the two-step deposition tech-nique resulting in defect density of107cm−3and surface roughness of 0.5 nm.The fully strainedSi0.5Ge0.5film with high crystal quality was epitaxiallygrown at temperatures below 450°C. The layer was sandwiched between theGe buffer and the top 20 nm Ge layer to be used as an etch-stop in the etch- back process. A highly selective etching method was developed to remove the3μm Ge buffer and 10nm SiGe film without damaging the 20 nm transferringGe layer.The Ge pFETs were fabricated at temperatures below 600°C so that theycould be compatible with the M3D integration. The back interface of thedevices depleted atVBG= 0V, which confirmed the small density of fixedcharges at the Ge/BOX interface along with a low level of residual doping inthe Ge channel. The Ge pFETs with 70 % yield over the whole wafer showed60 % higher carrier mobility than Si reference devices.Low-temperature epitaxial growth of Si passivation layer on Ge was de-veloped in this thesis. For electrical evaluation of the passivation layer,metal-oxide-semiconductor (MOS) capacitors were fabricated and character-ized. The capacitors showed an interface trap density of3×1011eV−1cm−2,and hysteresis as low as 3 mV at Eox of 4MV/cm corresponding to oxide trapdensity of1.5×1010cm−2. The results indicate that this Si passivation layersubstantially improves the gate dielectric by reducing the subthreshold slopeof Ge devices while increasing their reliability. The in-situ doped SiGe layerwith a dopant concentration of2.5×1019cm−3and resistivity of 3.5 mΩcmwas selectively grown on Ge to improve the junction formation.The methods developed in this thesis are suitable for large-scale M3Dintegration of Ge pFET devices on the Si platform. The unique Ge layertransfer and etch-back techniques resulted in the fabrication of GOI substrateswith high thickness homogeneity, low residual doping, and sufficiently goodGe/BOX interface. The process temperatures for Ge transfer and pFETsfabrication are kept within the range of the M3D budget. Integration of theSi cap for gate dielectric formation and SiGe layers in the source/drain regionmay increase device performance and reliability
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