| 1. |
- Abd El Ghany, M. A., et al.
(author)
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High throughput architecture for CLICHÉ network on chip
- 2009
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In: Proceedings - IEEE International SOC Conference, SOCC 2009. - 9781424452200 ; , s. 155-158
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Conference paper (peer-reviewed)abstract
- High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.
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| 2. |
- Abd El Ghany, M. A., et al.
(author)
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High throughput architecture for high performance NoC
- 2009
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In: ISCAS. - : IEEE. - 9781424438280 ; , s. 2241-2244
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Conference paper (peer-reviewed)abstract
- High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.
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| 3. |
- Abd El Ghany, M. A., et al.
(author)
-
Power efficient networks on chip
- 2009
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In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - 9781424450916 ; , s. 105-108
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Conference paper (peer-reviewed)abstract
- a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.
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