| 1. |
- Acharya, Sarthak
(author)
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An SBU fully additive production approach for Board-level Electronics Packaging (SBU-CBM Method)
- 2021
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Licentiate thesis (other academic/artistic)abstract
- The worldwide electronics market is focusing on developing innovative technologies that can lead to denser, more resilient, and tighter board-level integration. The consumer electronics market is trending toward miniaturization, with HDI-PCBs dominating. Electronics shrinking and scaling technology is the prime concern of all manufacturers. The PCBA industry is transforming its production practices which can reduce the solder joints, limit the usage of discrete and bulky components, reduce the packaging factor of printed boards by accommodating the maximum number of ICs, minimize the assembly span, optimize the latency, and so on. However, developments in production processes in the PCB manufacturing industry need more attention than those in Silicon-based (ICs) fabrications. One of the issues in PCB fabrication is utilizing conventional metallization approaches. The majority of manufacturers continue to use standard Copper(Cu) laminates on the base substrate and lithography methods to shape the structures.In recent manufacturing technologies, semi-Additive process (SAP) or modified-SAP (mSAP) methods are being adopted to replace traditional subtractive print-and-etch procedures. To scale down the Lines and Spaces (L\&S) on PCBs comparable to that of IC-level, most smartphone makers use Substrate-like PCB (SLP) using mSAP methods. However, subtractive patterning has been used in the intermediate stages of fabrication in those methods. This thesis demonstrates a fully additive selective metallization-based production approach to bridge this technology gap between IC-level and board-level fabrications. The fabrication process has given the name 'Sequential Build-Up Covalent Bonded Metallisation' (SBU-CBM) method.This dissertation presents a new approach to Cu metallization using a significant step reducing-pattern-transfer process. The patterning method activates a seed layer of CBM polymer chains on a polymer surface with optimal UV-Laser settings. This surface modification enables a strong Copper (Cu) bonding onto the modified surface by Cu-plating. The suggested approach generated a 2.5D surface pattern using a micrometer via laser ablation and subsequent sub-micrometer laser lithography. Furthermore, the surface characterization of each step involved in the fabrication process is analysed and presented to show the sequential growth of layers on top of each other. To investigate the mechanism of the process at the interfaces, characterizations such as EDS, SEM, and XRD characterizations were performed. This PCB manufacturing method can selectively add metallic layers to the finest feature sizes at considerably lower temperatures. Overall, the thesis has addressed two critical aspects i.e. miniaturization of interconnects at board-level and the feasibility of a fully-additive production approach for electronics packaging.First, a subtractive method is shown to achieve Copper interconnects with feature size 3.0$\mu$m. This miniaturization corresponds to 70\% reduction in the feature size from 20 $\mu$m to 3 $\mu$m. Next, the proposed additive production process has produced Cu interconnects with feature sizes of 2.5 $\mu$m L\&S and via of diameter 10 $\mu$m. The scaling of the interconnects was achieved by optimizing the process parameters involved in the proposed fabrication recipe.Second, the sequential build-up (SBU) procedure is adopted to realize the embedded passives with the minimum possible feature size ($<$ 10 $\mu$m). An embedded capacitor and a planar inductor were fabricated. The proposed method can be employed to achieve any desirable pattern on FR-4, and a few of them are shown in the thesis. This additive technique can further be investigated through electrical and reliability assessment to make it an industrially accepted method.
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| 2. |
- Acharya, Sarthak, et al.
(author)
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Fabrication Process for On-Board Geometries Using a Polymer Composite-Based Selective Metallization for Next-Generation Electronics Packaging
- 2021
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In: Processes. - : MDPI. - 2227-9717. ; 9:9
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Journal article (peer-reviewed)abstract
- Advancements in production techniques in PCB manufacturing industries are still required as compared to silicon-ICs fabrications. One of the concerned areas in PCBs fabrication is the use of conventional methodologies for metallization. Most of the manufacturers are still using the traditional Copper (Cu) laminates on the base substrate and patterning the structures using lithography processes. As a result, significant amounts of metallic parts are etched away during any mass production process, causing unnecessary disposables leading to pollution. In this work, a new approach for Cu metallization is demonstrated with considerable step-reducing pattern-transfer mechanism. In the fabrication steps, a seed layer of covalent bonded metallization (CBM) chemistry on top of a dielectric epoxy resin is polymerized using actinic radiation intensity of a 375 nm UV laser source. The proposed method is capable of patterning any desirable geometries using the above-mentioned surface modification followed by metallization. To metallize the patterns, a proprietary electroless bath has been used. The metallic layer grows only on the selective polymer-activated locations and thus is called selective metallization. The highlight of this production technique is its occurrence at a low temperature (20–45 °C). In this paper, FR-4 as a base substrate and polyurethane (PU) as epoxy resin were used to achieve various geometries, useful in electronics packaging. In addition, analysis of the process parameters and some challenges witnessed during the process development are also outlined. As a use case, a planar inductor is fabricated to demonstrate the application of the proposed technique.
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| 3. |
- Al-Maqdasi, Zainab, 1986-, et al.
(author)
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Conductive Regenerated Cellulose Fibers for Multi-Functional Composites : Mechanical and Structural Investigation
- 2021
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In: Materials. - Basel, Switzerland : MDPI. - 1996-1944. ; 14:7
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Journal article (peer-reviewed)abstract
- Regenerated cellulose fibers coated with copper via electroless plating process are investigated for their mechanical properties, molecular structure changes, and suitability for use in sensing applications. Mechanical properties are evaluated in terms of tensile stiffness and strength of fiber tows before, during and after the plating process. The effect of the treatment on the molecular structure of fibers is investigated by measuring their thermal stability with differential scanning calorimetry and obtaining Raman spectra of fibers at different stages of the treatment. Results show that the last stage in the electroless process (the plating step) is the most detrimental, causing changes in fibers’ properties. Fibers seem to lose their structural integrity and develop surface defects that result in a substantial loss in their mechanical strength. However, repeating the process more than once or elongating the residence time in the plating bath does not show a further negative effect on the strength but contributes to the increase in the copper coating thickness, and, subsequently, the final stiffness of the tows. Monitoring the changes in resistance values with applied strain on a model composite made of these conductive tows show an excellent correlation between the increase in strain and increase in electrical resistance. These results indicate that these fibers show potential when combined with conventional composites of glass or carbon fibers as structure monitoring devices without largely affecting their mechanical performance.
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| 4. |
- Khan, Sajid, et al.
(author)
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D flip-flop based TRNG with zero hardware cost for IoT security applications
- 2021
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In: Microelectronics and reliability. - : Elsevier. - 0026-2714 .- 1872-941X. ; 120
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Journal article (peer-reviewed)abstract
- System-on-chips (SoCs) for the Internet of things (IoT) applications require hardware-based integrated random number generators for the secure transmission of information. However, they have limited hardware and power budget, which limits the use of on-chip dedicated True Random Number Generator (TRNG). In this work, a symmetric D flip-flop with integrated TRNG is proposed. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers good randomness with low energy-per-bit. In addition, the circuit has passed all the tests of NIST without any post-processing. When compared with the conventional D flip-flop, it has almost negligible area overhead that is only 0.14%. An FPGA implementation is also presented as a proof of concept that confirms the simulation results. Advanced Encryption Standard (AES) key expansion algorithm is also implemented to demonstrate the dual usage of the proposed D flip-flop.
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| 5. |
- Sharma, Vishal, et al.
(author)
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A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes
- 2021
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In: Analog Integrated Circuits and Signal Processing. - : Springer. - 0925-1030 .- 1573-1979. ; 107:2, s. 339-352
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Journal article (peer-reviewed)abstract
- The work proposes an 11T SRAM cell which confirms its reliability for Internet of Things (IoT) based health monitoring system. The cell executes improved write and read ability using data-dependent feedback cutting and read decoupled access path mechanism respectively. The write and read stabilities of proposed cell are 2.67× and 1.98× higher than the conventional 6T cell with 1.53× area overhead. Moreover, the improved soft error tolerance and better reliability against negative bias temperature instability (NBTI) of proposed 11T SRAM cell as compared to other considered cells make it suitable for the bio medical implant. A low-power double adjacent bit error detection and correction (DAEDC) scheme is proposed to further improve the robustness of designed 1 Kb bit-interleaved memory against the soft error occurrence. The leakage power of proposed cell is controlled by the stacking devices used in its cross-coupled inverter pair and the column based read ground signal (RGND) further controls the unnecessary bit line switching power of the array.
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