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Search: WFRF:(Ellervee Peeter) > (2020-2024)

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1.
  • Gannedahl, Rikard, et al. (author)
  • A mm-Wave Differential-to-Quadrature Frequency Tripler with Automatic Locking and Quadrature Correction
  • 2023
  • In: 2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings. - 9798350337570
  • Conference paper (peer-reviewed)abstract
    • This paper presents an injection-locked frequency tripler for 28-GHz direct-conversion transceivers, which takes a differential input and outputs a quadrature signal. A feedback system is added to ensure that lock occurs and to keep the quadrature error below 1° across operating frequencies and process corners. Simulations show that the tripler can cover the entire 24-30 GHz band across all corners, while consuming 32 mW from a 0.8 V supply. The circuit is designed and simulated in a 22nm FD-SOI CMOS process and occupies 0.2 mm2 active chip area.
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2.
  • Karrari, Hamid, et al. (author)
  • A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS
  • 2023
  • In: 2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings. - 9798350337570
  • Conference paper (peer-reviewed)abstract
    • This paper presents a 4-channel time-interleaved (TI) analog-to-digital converter (ADC), where each channel is comprised of a two-stage pipelined asynchronous successive-approximation (ASAR) sub-ADC. The ADC employs two samplers to alleviate the problem of timing skew on the sub-sampler when distributing the clock to the TI channels. To further increase the speed of the ADC, the reset switch in the capacitive digital-to-analog converter of each sub-ADC is also boot-strapped. The ADC is implemented in a 22-nm CMOS FDSOI technology. With a sampling rate of 1.4 GS/s, measurements show that the ADC achieves an SNDR of 50 dB with a low-frequency input. The SNDR drops by only 1.5 dB at Nyquist. Powered by a 0.8 V supply, the total power consumption of the ADC is 37.5 mW, while the ADC core consumes 19.3 mW.
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3.
  • Moraitis, Michail, 1994- (author)
  • Towards Securing the FPGA Bitstream: Exploiting Vulnerabilities and Implementing Countermeasures
  • 2024
  • Doctoral thesis (other academic/artistic)abstract
    • Field-programmable gate arrays (FPGAs) are used across various industries due to their high performance, energy efficiency, and reconfigurability. However, the major advantage of reconfigurability is also a source of security challenges.The present doctoral thesis investigates the security vulnerabilities of the FPGA configuration file, i.e. the bitstream, focusing on the exploration and mitigation of targeted bitstream modification attacks. The results outlined in the seven chapters of the thesis are based on the appended collection of twelve papers. Out of those papers, seven present novel research on the topic of bitstream modification attacks and countermeasures, with the majority of contributions being on attacks. Four present novel research on the topic of FPGA-based countermeasures against side-channel analysis. The final paper presents a survey on bitstream modification attacks and countermeasures. The motivation behind the papers on side-channel countermeasures is to enhance the FPGA encryption schemes, as strong encryption can thwart targeted bitstream modification attacks. The attack vector of targeted bitstream modification is explored through a series of attacks against cryptographic FPGA implementations. The targets are popular stream ciphers (SNOW 3G, ACORN, and Trivium) and cryptographic primitives (an arbiter-based physical unclonable function and multi-ring-oscillator-based true random number generator). In the attacks on stream ciphers, the bitstream is modified to introduce faults that weaken the keystream by linearizing its generation process. A subsequent analysis of that faulty keystream reveals the secret key of the implementations. In the attacks on cryptographic primitives, the goal of the bitstream modification attack is to lower the bar or enable a side-channel analysis. The aim of the side-channel analysis is to predict the random output values produced by the primitives. To facilitate that, the bitstream modification attack identifies components in the bitstream that produce exploitable information leakage and creates multiple copies of them. The copies have the same values as the targets, but their outputs are not connected, thus having no impact on the functionality of the design. The study on bitstream modification is complemented with the introduction of low-cost obfuscation countermeasures and a general-purpose methodology against obfuscation based on constants. The methodology is able to defeat all the countermeasures we have previously defined, and its application extends to the general field of hardware design obfuscation.On the topic of side-channel analysis countermeasures, the popular methodology of clock randomization is evaluated. The assumed side-channel analysis aims to extract the secret key of the advanced encryption standard (AES) block cipher. The evaluation reveales that clock randomization cannot offer protection when the side-channel measurements are sampled at a frequency significantly higher than the operational frequency of the device. In response to that, the clock randomization technique is coupled with encryption core duplication to form, a novel countermeasure called CRCD (clock randomization with encryption core duplication). The countermeasure is shown to effectively protect implementations of block ciphers such as AES, and post-quantum key encapsulation mechanisms such as CRYSTALS-Kyber. Further analysis of the countermeasure reveals a weakness that is exploited and finally patched in an updated implementation of CRCD.
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