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- Fu, Jing, et al.
(author)
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Designing and Evaluating Network Processor Applications
- 2005
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In: IEEE Workshop on High Performance Switching and Routing. ; , s. 142-146
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Conference paper (peer-reviewed)abstract
- Network processors try to achieve the performance of traditional ASICs while providing programmability of general-purpose processors. In short, a network processor provides a programming interface for implementing packet forwarding services. It is therefore important to study how efficient different designs are, as well as investigate how difficult they are to program. In this paper, a network processor model is introduced which is used as a basis for a simulation tool. By sending packets into the simulator, throughput, latency, and utilization can be measured. An IPv4 forwarding application is evaluated using two different processing element topologies: a pipelined and a pooled. In addition, the performance impact of using multiple threads inside a single processing element is evaluated. The results show that the use of parallelism is crucial to achieve high performance, but that both the pipelined topology and pooled topology achieve comparable performance.
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- Fu, Jing, et al.
(author)
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Improving and Analyzing LC-Trie Performance for IP-Address Lookup
- 2007
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In: Journal of Networks. - : Academy Publisher. - 1796-2056. ; 2:3, s. 18-27
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Journal article (peer-reviewed)abstract
- IP-address lookup is a key processing function of Internet routers. The lookupis challenging because it needs to perform a longest prefix match. In this paper, wepresent our modifications to an efficient lookup algorithm, the LC-trie, based ona technique called prefix transformation. Thereafter, the LC-trie’s performance isanalyzed for both the original and our modified algorithm using real and syntheticallygenerated traces. The performance study includes trie search depth, prefixvector access behavior, cache behavior and packet lookup time. The study is basedboth on experiments and a model for packet lookup time. The results show thatthe modified algorithm requires only 30% of the lookup time of the original algorithm.In particular, the modified algorithm is capable of performing 60 millionpacket lookups per second on a Pentium 4, 2.8 GHz, computer for a real traffictrace. Further, the results show that the performance is about five times better onthe real trace compared to a synthetically generated network trace. This illustratesthat the choice of traces may have a large influence on the results when evaluatinglookup algorithms.
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- Fu, Jing, et al.
(author)
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Performance Evaluation and Cache Behavior of LC-Trie for IP-Address Lookup
- 2006
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In: Proc. of IEEE 2006 Workshop on High Performance Switching and Routing (HPSR 2006). - : IEEE. - 0780395697 - 9780780395695 ; , s. 29-35
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Conference paper (peer-reviewed)abstract
- Many IP-address lookup software algorithms use a trie-like data structure to perform longest prefix match. LC-trie is an efficient algorithm that uses level compression and path compression on tries. By using realistic and synthetically generated traces, we study the performance of the LC-trie algorithm. Our study includes trie search depth, prefix vector access behavior, cache behavior, and packet lookup service time. The results show that for a realistic traffic trace, the LC-trie algorithm is capable of performing 20 million packet lookups per second on a Pentium 4, 2.8 GHz computer, which corresponds to a 40 Gb/s link for average sized packets. Further, the results show that LC-trie performs up to five times better on the realistic trace compared to a synthetically generated network trace. This illustrates that the choice of traces may have a large influence on the results when evaluating lookup algorithms.
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- Fu, Jing, et al.
(author)
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Queueing Behavior and Packet Delays in Network Processor Systems
- 2007
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In: 15th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems. - 9781424418534 ; , s. 217-224
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Conference paper (peer-reviewed)abstract
- Network processor systems provide the performance of ASICs combined withthe programmability of general-purpose processors. One of the main challengesin designing these systems is the memory subsystem used when forwarding andqueueing packets. In this work, we study the queueing behavior and packet delaysin a network processor system which works as a router. We introduce a systemmodel and a simulation tool based on the model. Using the simulation tool, bothbest-effort and diffserv IPv4 forwarding were modeled and tested using real-worldand synthetically generated packet traces. The results on queueing behavior havebeen used to dimension various queues, and can be used as guidelines for designingmemory subsystems and queueing disciplines. In particular, a system withsmall queue sizes has been proposed. The results on packet delays also show thatour diffserv setup provides good service differentiation for best-effort and prioritypackets. Finally, the study reveals that the choice of traces has a large impact onthe results when evaluating router and switch architectures.
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- Hagsand, Olof, et al.
(author)
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Design and implementation of a distributed router
- 2005
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In: 2005 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), Vols 1 and 2. - 0780393139 ; , s. 227-232
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Conference paper (peer-reviewed)abstract
- The requirements on 1P routers are increasing for every new generation of designs. The driving forces are growing traffic volumes and demands for new services. We argue that a decentralized modular system design would improve the scalability. flexibility, and reliability of future routers. We have designed and implemented such a distributed router. based on physical separation between different junctional modules for control and forwarding plane operations. This paper presents the design and implementation, focusing on the internal communication protocols and implementation aspects of the control plane.
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- Hagsand, Olof, et al.
(author)
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Open source routing at 10Gb/s
- 2009
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In: Swedish National Computer Networking Workshop, SNCNW 2009, Uppsala, Sweden.
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Conference paper (peer-reviewed)abstract
- We present throughput measurements using the Bifrost Linux open source router on selected PC hardware. The hardware consists of eight CPU cores, NUMA architecture, double PCIe buses and Intel and SUN 10Gb/s interface cards. These cards are equipped with hardware classifiers that dispatch packets to multiple DMA queues which enables parallel processing of packet forwarding and load-balancing between the multiple CPUs. In our experiments, we send a multiflow, simplex packet stream through an open-source router. We measure the throughput and vary packet size, active CPUs, and router configuration. In the experiments, we use an IP flow and packet-length distribution that we claim is realistic for many network scenarios. Using these realistic traffic streams, we show how speeds close to10Gb/s is achievable for normal Internet traffic. In particular, we show how the use of multiple CPUs increases the throughput up to a breakpoint which in our setting is at four CPUs. Further, we show that adding filters and full BGP tables have minor effects in the performance. With these results, we claim that open source routers using new PC architectures are a viable option for use in 10Gb/s networks for many network scenarios.
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