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| 2. |
- Grange, Matt, et al.
(author)
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Examination of Delay and Signal Integrity Metrics in Through Silicon Vias
- 2009
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In: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Electronic Workshop Digest, Palais des Congrès Acropolis – Nice, France, Friday April 24, 2009. - Nice, France. ; , s. 260-264
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Conference paper (peer-reviewed)abstract
- This article discusses results from simulations of signaling in Through Silicon Vias (TSVs) with an emphasis on latency and signal integrity effects. Data from field solver simulations is used for TSV parasitics and employed in SPICE simulations. A reduced order electrical circuit is proposed for lone TSVs as well as bundled structures and switch-factor based delay models are derived to calculate rise times in a 3x3 bundle. Furthermore Signal Integrity (SI) issues in coupled TSVs are briefly discussed.
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| 3. |
- Grange, Matt, et al.
(author)
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Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
- 2009
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In: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
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Conference paper (peer-reviewed)abstract
- The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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| 4. |
- Nurmi, T., et al.
(author)
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Global interconnect analysis
- 2005
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In: Interconnect-Centric Design for Advanced SoC and NoC. - Boston : Springer Science+Business Media B.V.. - 9781402078354 - 9781402078361 ; , s. 55-84
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Book chapter (peer-reviewed)abstract
- The rapid development in deep submicron (DSM) technology makes possible to design complex billion-transistor chips. To take full advantage of increased integration density and cope with the difficulties in designing such complex systems, the emphasis of design methodology has changed from gate-level design to the exploitation of intellectual property (IP) blocks. This IP-based design is rapidly becoming the dominating design paradigm in System-on-Chip (SoC) era. IP blocks themselves are usually verified by the supplier for some technology node but the problem is how to ensure the correct performance when the IP block is integrated in the SoC or even in Network-on-Chip (NoC) environment. The problems occur in adapting the block interface into the used communication frame. The main objective is to make computation (IP blocks) and communication independent on each other. Due to increasing integration density and diminishing wire dimensions, communication using traditional SoC interconnect schemes (such as buses) does not scale up properly compared with system complexity. This leads to the communication scheme where traditional buses and their arbitration are replaced with network switches connecting various IP blocks in different network nodes to each other. Thus, a shift from SoC to NoC is predicted when system complexity scales up on chip level. Network nodes bring inherent pipelining and buffering onto system level which is important when dealing with global wires that have more resistive and inductive nature in current and future DSM technologies. Additionally, undesired transmission errors can be reduced with errorchecking, e.g. in each network node. In this case, latency may increase as a result of increased reliability. In this chapter, we first discuss parasitic modeling in the presence of crosstalk and delay modeling of global wires. Inductance issues are discussed in more detail in chapter 5 and thus we omit them here. Some possible interconnect schemes in SoC and NoC are shortly discussed. In section 3.3 we evaluate cost functions (e.g. power consumption and area) that IP blocks set for the global communication network. We present a method how to evaluate those costs in the early phase of design. By evaluating costs of those resources we can better optimize global interconnects to meet both signal and power distribution challenges. We present one case study example on the cost evaluation. Finally, in section 3.4 we apply methods and theories presented in earlier sections and optimize global interconnects to meet different constraints. The delay in global wires is optimized using repeaters that are sized properly and placed in proper distances so that the overall delay is optimized. Then we present optimal signaling having maximum throughput as a constraint. Last, we present a case study in which both power and signal distribution are simultaneously optimized. This is done by using a method called interconnect partitioning and the design constraint in this case is the maximum allowed variation of power supply levels in the power distribution network. The variation depends on the grain size of the power distribution grid and power consumption taking place in IP (or functional) blocks due to simultaneous switching of large amount of logic gates in a very short time interval.
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| 5. |
- Pamunuwa, Dinesh, et al.
(author)
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Modeling or delay and noise in arbitrarily coupled RC trees
- 2005
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In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070 .- 1937-4151. ; 24:11, s. 1725-1739
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Journal article (peer-reviewed)abstract
- Closed-form equations for second-order transfer functions of general arbitrarily coupled resistance-capacitance (RC) trees with multiple drivers are reported. The models allow precise delay and noise calculations for systems of coupled interconnects with guaranteed stability and represent the minimum complexity associated with this class of circuits. Their accuracy is extensively compared against other relevant models and is found to be better or comparable to more expensive models. All results are derived from a theoretical approach, and their physical basis is examined. The simplicity, accuracy, and generality of the models make them suitable for use in early signal integrity analyses of complex systems and incremental physical optimization.
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| 6. |
- Pamunuwa, Dinesh, et al.
(author)
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Nanodevices : from novelty toys to functional devices - an integration perspective
- 2006
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In: First International Conference on Industrial and Information Systems. - Peradeniya, Sri Lanka. - 1424403227 ; , s. 103-108
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Conference paper (peer-reviewed)abstract
- This paper looks at the prospects of continuing Moore’s law into the deca nanometer regime using novel technology that has been recently proposed in the literature. It reviews some key advances in nanoelectronics, and provides an integration perspective for the ultimate goal of terascale integration. Issues from physical level circuits to system level architectures are discussed.
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| 7. |
- Pamunuwa, Dinesh, et al.
(author)
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The Memory Challenge in NoC Based Systems
- 2008
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In: Proc. Design, Automation and Test in Europe Conference (DATE), hot topic session. ; , s. 1126-1127
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Conference paper (other academic/artistic)
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| 8. |
- Weerasekera, Roshan, et al.
(author)
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Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits
- 2009
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In: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - NEW YORK : IEEE. - 9781424445110 ; , s. 322-329
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Conference paper (peer-reviewed)abstract
- Modeling parasitic parameters of Through-Silicon-Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) Integrated Circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for resistance, capacitance and inductance of various TSV structures. Further, a reduced-order electrical circuit model is proposed for isolated TSVs as well as bundled structures for delay and SI analysis, and extracted TSV parasitics are employed in Spectre simulations for performance evaluations. Critical issues in the performance modeling for design space exploration of 3-D ICs such as crosstalk induced switching pattern dependent delay variation and cross-talk on noise are discussed. The error in these metrics when using the proposed models as compared to a field solver is contained to a few percentage points.
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| 9. |
- Weerasekera, Roshan, et al.
(author)
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Delay-balanced smart repeaters for on-chip global signaling
- 2007
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In: 20th International Conference On VLSI Design, Proceedings. - 9780769527628 ; , s. 308-313
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Conference paper (peer-reviewed)abstract
- In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18 mu m technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.
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| 10. |
- Weerasekera, Roshan, et al.
(author)
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Early selection of system implementation choice among SoC, SoP and 3-D integration
- 2007
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In: Proceedings - 20th Anniversary IEEE International SOC Conference. - 9781424415922 ; , s. 187-190
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Conference paper (peer-reviewed)abstract
- Recently there is a tendency for shifting the planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration, and the designers confronted with several system design options. To get a true improvement in performance, a very careful analysis using detailed models at different hierarchical levels is crucial. In this work, we present a cohesive analysis of the technological, cost and performance trade-offs for implementing digital and mixed-mode systems considering the choices between 2-D and 3-D integration and their ramifications.
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