| 1. |
- Abdulaziz, Mohammed, et al.
(author)
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A 3.4mW 65nm CMOS 5th Order Programmable Active-RC Channel Select Filter for LTE Receivers
- 2013
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In: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013. - 1529-2517. - 9781467360593 ; , s. 217-220
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Conference paper (peer-reviewed)abstract
- In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm CMOS technology with a core area of 0.29mm2. Its total current consumption is 2.83mA from a 1.2V supply. The measured input referred noise is 39nV/ √ Hz, the in-band IIP3 is 21.5dBm, at the band-edge the IIP3 is 20.7dBm, the out-of-band IIP3 is 20.6dBm, and the compression point is 0dBm.
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| 2. |
- Abdulaziz, Mohammed, et al.
(author)
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A 4th Order Gm-C Filter with 10MHz Bandwidth and 39dBm IIP3 in 65nm CMOS
- 2014
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In: [Host publication title missing]. - 1930-8833. ; , s. 367-370
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Conference paper (peer-reviewed)abstract
- Gm-C filters suffer from limited dynamic range due to a trade-off between noise and linearity in OTA design. This paper therefore presents a filter with a linearization technique to break this trade-off. This technique is demonstrated by a low power 4th order 10MHz Butterworth Gm-C low pass filter. The filter was implemented in 65nm CMOS technology with a core area of 0.19mm2 and a total current consumption of 3.5mA from a 1.2V supply. The measured input referred noise is 31nV/√Hz, the maximum in-band IIP3 is 39dBm, the out-of-band IIP3 is 34dBm, and the compression point is 8.2dBm.
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| 3. |
- Abdulaziz, Mohammed, et al.
(author)
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A Compensation Technique for Two-Stage Differential OTAs
- 2014
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In: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 61:8, s. 594-598
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Journal article (peer-reviewed)abstract
- In this paper a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole.The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values which makes it attractive for low power applications with low area overhead.
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| 4. |
- Ahmad, Waqas, et al.
(author)
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A Fully Integrated Radio-Fiber Interface in 65 nm CMOS Technology
- 2014
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In: IEEE Photonics Technology Letters. - 1041-1135. ; 26:5, s. 444-446
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Journal article (peer-reviewed)abstract
- In this work we present a fully integrated Radio-Fiber interface implemented in 65nm CMOS, intended for remote antenna units (RAUs) in distributed antenna systems. To relax the requirements on the optical components, an intermediate frequency (IF) signal (100MHz) is transmitted over the multi-mode fiber, which is then up-converted to 2.2GHz inside the RAU. Local Oscillator (LO) signals to the mixers are generated by an on-chip frequency synthesizer. The measured optical to electrical conversion gain\,(V/W) is 59\,dB, whereas the input referred current noise is 3.5pA/$\sqrt{\mathrm{Hz}}$ and SFDR is 96.5dBHz^2/3. An LO leakage of -40dBc and an image rejection ratio of 43\,dB is measured. The circuit achieves an adjacent channel leakage ratio (ACLR) of -39dB and -41dB, for a 10MHz 32QAM signal at output power of 1dBm, and a 3.84MHz QPSK signal at 4dBm, respectively.
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| 5. |
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| 6. |
- Ahmad, Waqas, et al.
(author)
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Fully Integrated Radio over Fiber Downlink for Distributed Multi-antenna Systems in 65nm CMOS
- 2014
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In: 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS). - 9781479978694 ; , s. 353-356
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Conference paper (peer-reviewed)abstract
- This paper presents a fully integrated downlink for low-cost remote antenna units in fiber-fed distributed multi-antenna systems. To reduce the cost of optical parts, an intermediate frequency(IF) signal is distributed over the fiber, and the circuit consists of an optical receiver, a single side-band frequency up-converting radio transmitter, and LO generation circuitry. The optical to electrical conversion gain(V/W) of the system is 59dB, and an output referred 1dB compression point of +6dBm and an OIP3 of +17dBm are measured. The SFDR of the circuit is 96.5 dBHz^2/3. The phase noise of the PLL measured at 4.2GHz is -145dBc/Hz at 20MHz offset, where as the reference spur level is -58dBc. The circuit is fabricated in a standard 65nm CMOS process and occupies just 0.8mm^2 of chip area including bond pads.
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| 7. |
- Ahmad, Waqas, et al.
(author)
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Performance evaluation of N-well/P-sub photodiodes in 65nm CMOS process
- 2013
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In: [Host publication title missing]. - 9781479904648 ; , s. 135-136
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Conference paper (peer-reviewed)abstract
- This work explores the n-well/p-substrate photodiode in a deep submicron CMOS process. A CMOS chip is designed featuring different structures of the photodiode. When characterized at a wavelength of 850nm DC responsivities between 0.12 and 0.16 A/W and 3-dB bandwidths of about 6 MHz with a roll-off of about 5.5dB/decade are measured. These investigations are very useful in designing the transimpedance amplifier and equalizer for a fully integrated optical receiver. According to the authors’ knowledge it is the first reported study on n-well/p-sub photodiodes in a 65nm CMOS technology.
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| 9. |
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| 10. |
- Amirkhanzadeh, Robabeh, et al.
(author)
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L-Band 180 degree passive phase shifter employing auto-tranformer in an SOS process
- 2014
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In: Proc. of International Symposium on Circuits and systems (ISCAS). - 9781479934317 ; , s. 333-336
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Conference paper (peer-reviewed)abstract
- In this paper, we present a new topology to implement a passive 180° phase shifter using on-chip auto-transformer in an SOS process. The measured results indicate a phase variation of less than 2° over the frequency range of 1.8-2.4GHz. An insertion loss of 2.3dB was measured at 2.1GHz. The phase shifter has a small footprint of 0.3 × 0.7mm2, which is almost three times less than a traditional high-pass/low-pass design. Post-layout simulations indicate similar performance in terms of bandwidth, phase accuracy and insertion loss for both circuits. Stacked switches are used to increase the power handling to +20dBm.
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