| 1. |
- Albrecht, Steffen, et al.
(author)
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A Frequency Synthesizer Architecture Using Frequency Difference Detection
- 2003
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Conference paper (peer-reviewed)abstract
- In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.
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| 2. |
- Ben Dhaou, Imed, et al.
(author)
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Comparison of OFDM and WPM for fourth generation broadband WLAN
- 2000
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In: European Signal Processing Conference.
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Conference paper (peer-reviewed)abstract
- In this paper, we propose a qualitative comparison between OFDM (Orthogonal Frequency Division Multiplexing), and WPM (Wavelet Packet Modulation). The comparison is done for two separate cases. Firstly, the efficiency of the two signaling systems will be compared. Secondly, the requirements for hardware implementation will be performed. From the performance and the VLSI implementation viewpoint, we found that WPM outperforms OFDM. However, the out-of-band radiation and peak-to-average-power for the case of OFDM is better compared to the WPM. The extensive simulation results, show that the average increase of peak-to-average-power is approximately 0.98dB compared to the OFDM. The increase of the adjacent channel power ratio channel is approximately 12.41dBc compared to the OFDM.
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| 3. |
- Ben Dhaou, I., et al.
(author)
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Current mode, low-power, on-chip signaling in deep-submicron CMOS technology
- 2003
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In: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268. ; 50:3, s. 397-406
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Journal article (peer-reviewed)abstract
- qThis paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10% Experimental results on a set of benchmark signaling problems implemented in a 0.25-mum 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a twofold reduction in the power and a reduction of 1.4 times the area.
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| 4. |
- Ben Dhaou, I., et al.
(author)
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Efficient library characterization for high-level power estimation
- 2004
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In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210 .- 1557-9999. ; 12:6, s. 657-661
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Journal article (peer-reviewed)abstract
- This paper describes LP-DSM, which is an algorithm used for efficient library characterization in high-level power estimation. LP-DSM characterizes the power consumption of building blocks using the entropy of primary inputs and primary outputs. The experimental results showed that over a wide range of benchmark circuits implemented using full custom design in 0.35-mum 3.3 V CMOS process the statistical performance (mean and maximum error) of LP-DSM is comparable or sometimes better than most of the published algorithms. Moreover, it was found that LP-DSM has the lowest prediction sum of squares, which makes it an efficient tool for power prediction. Furthermore, the complexity of the LP-DSM is linear in relation to the number of primary inputs (O(NI)), whereas state of the art published library characterization algorithms have a complexity of O(NI2).
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| 5. |
- Ben Dhaou, I., et al.
(author)
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Energy efficient signaling in deep-submicron technology
- 2002
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In: VLSI design (Print). - : Hindawi Limited. - 1065-514X .- 1563-5171. ; 15:3, s. 563-586
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Journal article (peer-reviewed)abstract
- In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption. In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires. The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.
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| 6. |
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| 7. |
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| 8. |
- Duo, Xinzhong, et al.
(author)
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A DC-13GHz LNA for UWB RFID applications
- 2004
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In: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - 0780385101 ; , s. 241-244
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Conference paper (peer-reviewed)abstract
- In this paper, we present a 4-stage traveling wave lownoise amplifier for UWB RFID (ultra-wideband radiofrequency identification). This LNA covers a frequencyrange of DC - 13 CHz. The circuit is implemented with0.I5pm GaAs PHEMT chips embedded in flexible LCP(liquid crystal polymer) substrate. In the frequency range,the gain of the LNA is better than IO dB, fluctuation of thegain is less than 3dB, its noise figure is less than 4dB, SI 1and S22 are around -10 dB.
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| 9. |
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| 10. |
- Duo, Xinzhong, et al.
(author)
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Analysis of lossy packaging parasitics for common emitter LNA in system-on-package
- 2004
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In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING. - NEW YORK : IEEE. - 0780386671 ; , s. 75-78
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Conference paper (peer-reviewed)abstract
- Advances of VLSI and packaging technologies enable condensed integration of an RF system in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP for RF systems and their sub-systems, it is needed to predict and estimate performance of each solution. In this paper, analytical equations for noise figure and gain of inductively degenerated common-emitter low-noise amplifiers in SoP/SoC are deduced as functions of passives and packaging parasitics. They hence enable designers to evaluate overall performance of each solution quantitatively. As well, influence of lossy packaging parasitics on LNA is also analyzed.
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