| 1. |
- Caputa, Peter, 1973-
(author)
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Design of efficient high-speed on-chip global interconnects
- 2004
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Licentiate thesis (other academic/artistic)abstract
- The development of integrated circuits is continuously moving towards a System-on Chip realization where global interconnects, connecting circuit blocks separated by a long distance, have been considered a showstopper for process scaling due to their RC-delays. Our knowledge today is that high-speed interconnects must be described by models which include not only R and C, but also inductance and skin effect. One might think that this will make the situation worse, but we show that it is not so.In this thesis, we investigate the relevance of inductance in interconnect models and propose a new scheme for global interconnects based on the utilization of microstrip lines using two upper-level metal layers, one thicker layer for wires and one for a return ground plane. We are concerned with key performance measures such as data delay, maximum data-rate, crosstalk, edge-rates and power dissipation. Using our approach, we show that well-designed, highly lossy, long interconnects may show reasonable delays of the order of twice the delay compared to the velocity of light delay, and allow high data rates disconnected from total delay through wave pipelining. To demonstrate the feasibility of the proposed concept, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over this 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 µm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition energy cost model aimed for efficient power estimation of performance-critical buses. The model, which includes properties that closely capture effects present in high performance VLSI buses, can be used to more accurately determine energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a cache bus architecture used in industry.
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| 2. |
- Duo, Xinzhong, et al.
(author)
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A DC-13GHz LNA for UWB RFID applications
- 2004
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In: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - 0780385101 ; , s. 241-244
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Conference paper (peer-reviewed)abstract
- In this paper, we present a 4-stage traveling wave lownoise amplifier for UWB RFID (ultra-wideband radiofrequency identification). This LNA covers a frequencyrange of DC - 13 CHz. The circuit is implemented with0.I5pm GaAs PHEMT chips embedded in flexible LCP(liquid crystal polymer) substrate. In the frequency range,the gain of the LNA is better than IO dB, fluctuation of thegain is less than 3dB, its noise figure is less than 4dB, SI 1and S22 are around -10 dB.
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| 3. |
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| 4. |
- Duo, Xinzhong, et al.
(author)
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Analysis of lossy packaging parasitics for common emitter LNA in system-on-package
- 2004
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In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING. - NEW YORK : IEEE. - 0780386671 ; , s. 75-78
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Conference paper (peer-reviewed)abstract
- Advances of VLSI and packaging technologies enable condensed integration of an RF system in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP for RF systems and their sub-systems, it is needed to predict and estimate performance of each solution. In this paper, analytical equations for noise figure and gain of inductively degenerated common-emitter low-noise amplifiers in SoP/SoC are deduced as functions of passives and packaging parasitics. They hence enable designers to evaluate overall performance of each solution quantitatively. As well, influence of lossy packaging parasitics on LNA is also analyzed.
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| 5. |
- Duo, Xinzhong, et al.
(author)
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Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis
- 2003
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In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING. - NEW YORK : IEEE. ; , s. 55-58
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Conference paper (peer-reviewed)abstract
- In this paper, we present common emitter LNAs (low noise amplifiers) in system-on-package for 5GHz WLAN application. Innovation of this module is that it is chip-package co-designed and co-simulated with performance trade-offs for on-chip versus off-chip passive component integration. It thus provides an optimal total solution for embedded RF electronics in system-level integration. Analytical equations for key performance parameters, noise figure and gain, of these LNAs are developed as functions of quality factors of passive components and the package parasitics. They hence provide designers a quantitative trade-off for on-chip versus off-chip passive components integration in SoP design. The final module is composed of on-chip active components in 0.5mum SiGe BiCMOS technology and off-chip passive components integrated in MCM-D substrate. Significant improvement in performance is found in these co-designed LNAs than those in single-chip LNAs.
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| 6. |
- Duo, Xinzhong, et al.
(author)
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Design and implementation of a 5GHz RF receiver front-end in LCP based system-on-package module with embedded chip technology
- 2003
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In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING. - 0780381289 ; , s. 51-54
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Conference paper (peer-reviewed)abstract
- In this paper, we present a receiver front-end for 5 GHz wireless LAN in novel LCP (liquid crystal polymer) based system-on-package module. The module is based on embedded chip technologies for system-on-package, which eliminates the constraints of off-chip pad drive capability and hence improves electrical performance. Furthermore, the novel LCP material shows excellent RF and microwave performance. The quality factors of key passive components such as inductors integrated in LCP substrate with thin film technologies is as high as 60. The insertion loss of the bandpass filter is 3dB. The conversion gain of the receiver front-end is 20 dB and occupies 8.7mm by 3.6mm area.
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| 7. |
- Duo, Xinzhong, et al.
(author)
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Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips
- 2003
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In: Analog Integrated Circuits and Signal Processing. - GZ DORDRECHT : KLUWER ACADEMIC PUBL. - 0925-1030 .- 1573-1979. ; 34:1, s. 39-47
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Journal article (peer-reviewed)abstract
- In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP) RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic) simulations. The performance of spiral inductors fabricated with various geometrical and technological parameters was analyzed. It is shown that Q (the quality factor) and f(res) (the self-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line, which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embedded components, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Through this study, optimal structures for such components are identified and guidelines for design and fabrications are derived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful to determine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a long time.
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| 8. |
- Duo, Xinzhong, et al.
(author)
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On-chip versus off-chip passives analysis in radio and mixed-signal system-on-package design
- 2004
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In: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04). - NEW YORK : IEEE. - 0780386205 ; , s. 109-116
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Conference paper (peer-reviewed)abstract
- Advances of VLSI and packaging technologies enable condensed integration of system level functions in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP, and eliminate constraints between chip and package, a complete solution is needed to co-design and co-optimize chip and package in a total design plan with precise trade-offs of on-chip versus off-chip passives. In this paper, we present a complete and systematic design methodology for RF SoP/SoC. This methodology includes early analysis and design implementation. This early analysis is to estimate the performance and cost of each solution quickly and quantitively. Then, the best solution is found and implemented. For a better presentation, the method and design techniques are demonstrated through the design of a common emitter low noise amplifier (LNA) for 5GHz wireless LAN (local area network). Analytical equations of noise figure and transducer gain for the LNA with lossy package are also developed.
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| 9. |
- Duo, Xinzhong, et al.
(author)
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On-chip versus off-chip passives in multi-band radio design
- 2004
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In: ESSCIRC 2004. - NEW YORK : IEEE. - 0780384806 ; , s. 327-330
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Conference paper (peer-reviewed)abstract
- This paper presents on-chip versus off-chip passives in multi-band radio design. The analysis is demonstrated through several multi-band low noise amplifiers designs in SiGe BiCMOS and GaAs PHEMT. Cost-performance trade-off analysis shows that when on-chip passives are moved off chip, performance of RF circuits is always improved. However, simple RF circuits do not show obvious cost-benefits, whereas complex RF circuits such as multi-band radio can have significant cost savings by using off-chip passives.
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| 10. |
- Duo, Xinzhong, et al.
(author)
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RF robustness enhancement through statistical analysis of chip-package co-design
- 2004
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In: 2004 IEEE International Symposium on Cirquits and Systems - Proceedings. - : IEEE. - 078038251X ; , s. 988-991
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Conference paper (peer-reviewed)abstract
- In order to enhance robustness of RF circuits, a flow of statistical analysis for chip-package co-design of RF system-on-package (SoP) is presented in this work. Methods for improving the yield of RF modules are developed. On-chip passive components versus off-chip passive components trade-offs in SoP module were also analyzed in terms of performance and yield. The design methods were demonstrated through case studies of LNA (low noise amplifier) in SoP.
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