| 21. |
- Fischer, Andreas C., 1982-, et al.
(author)
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3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching
- 2012
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In: Advanced Functional Materials. - : Wiley-VCH Verlagsgesellschaft. - 1616-301X .- 1616-3028. ; 22:19, s. 4004-4008
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Journal article (peer-reviewed)abstract
- A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro- and nanostructures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The method is demonstrated by fabricating 3D structures made of two and three silicon layers, including suspended beams that are 40 nm thick, 500 nm wide, and 4 μm long, and patterned lines that are 33 nm wide.
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| 22. |
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| 23. |
- Fischer, Andreas C., et al.
(author)
-
3D printing of silicon micro and nano structures by ion implantation, silicon deposition, and selective silicon etching
- 2013
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In: Technical Paper - Society of Manufacturing Engineers.
-
Conference paper (peer-reviewed)abstract
- A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro and nano structures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The proposed technology could change and greatly simplify the fabrication of many MEMS, NEMS, and silicon photonic devices without requiring a fully equipped semiconductor cleanroom. This layer-by-layer fabrication method is in principle also viable for the implementation of 3D structures in semiconductors other than silicon.
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| 24. |
- Fischer, Andreas C., 1982-, et al.
(author)
-
A method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device
- 2010
-
Patent (pop. science, debate, etc.)abstract
- A method for forming conductive vias in a substrate (302) by filling preformed via holes (303-305), preferably through via holes, with conductive material, comprises providing a plurality of preformed objects at least partly comprising ferromagnetic material (301) on a surface of the substrate; providing a magnetic source (307) on an opposite side of the substrate with respect to the plurality of preformed objects, thereby at least partly aligning at least a portion of the preformed objects with a magnetic field associated with the magnetic source; and moving the magnetic source relative the substrate, or vice versa, thereby moving the at least portion of the preformed objects into at least a portion of the via holes.
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| 25. |
- Fischer, Andreas C., et al.
(author)
-
Fabrication of high aspect ratio through silicon vias (TSVs) by magnetic assembly of nickel wires
- 2011
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In: Micro Electro Mechanical Systems (MEMS), 2011 IEEE 24th International Conference on. - : IEEE. - 9781424496327 ; , s. 37-40
-
Conference paper (peer-reviewed)abstract
- Three-dimensional (3D) integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies using through silicon vias (TSVs). They enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. This paper presents a novel low-cost fabrication technique for solid metal-filled TSVs using nickel wires as conductive path. The wires are placed in the via hole of a silicon wafer by magnetic self-assembly. This metal filling technique enables through-wafer vias with high aspect ratios and potentially eliminates characteristic cost drivers of the TSV production such as metallization processes, wafer thinning and general issues associated with thin-wafer handling.
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| 26. |
- Fischer, Andreas C., 1982-, et al.
(author)
-
Heterogeneous Integration for Optical MEMS
- 2010
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In: 2010 23RD ANNUAL MEETING OF THE IEEE PHOTONICS SOCIETY. - NEW YORK : IEEE. - 9781424453696 ; , s. 487-488
-
Conference paper (peer-reviewed)abstract
- In this paper we present different large-scale heterogeneous integration technologies for optical MEMS that enable the integration of optical MEMS with standard CMOS-based ICs. Examples that are presented include various monocrystalline silicon micro-mirror arrays and infrared bolometer arrays.
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| 27. |
- Fischer, Andreas C., 1982-, et al.
(author)
-
high aspect ratio tsvs fabricated by magnetic self-assembly of gold-coated nickel wires
- 2012
-
In: Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd. - : IEEE conference proceedings. - 9781467319652 ; , s. 541-547
-
Conference paper (peer-reviewed)abstract
- Three-dimensional (3D) integration is an emerging technologythat vertically interconnects stacked dies of electronics and/orMEMS-based transducers using through silicon vias (TSVs).TSVs enable the realization of devices with shorter signal lengths,smaller packages and lower parasitic capacitances, which can resultin higher performance and lower costs of the system. Inthis paper we demonstrate a new manufacturing technology forhigh-aspect ratio (> 8) through silicon metal vias using magneticself-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enablesthrough-wafer vias with high aspect ratios and superior electricalcharacteristics. This technique eliminates common issues inTSV fabrication using conventional approaches, such as the metaldeposition and via insulation and hence it has the potential to reducesignificantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications.
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| 28. |
- Fischer, Andreas C., et al.
(author)
-
Layer-by-layer 3D printing of Si micro- and nanostructures by Si deposition, ion implantation and selective Si etching
- 2012
-
In: 12th IEEE Conference on Nanotechnology (IEEE-NANO), 2012. - : IEEE conference proceedings. - 9781467321983 ; , s. 1-4
-
Conference paper (peer-reviewed)abstract
- In this paper we report a method for layer-by-layer printing of three-dimensional (3D) silicon (Si) micro- and nanostructures. This fabrication method is based on a sequence of alternating steps of chemical vapor deposition of Si and local implantation of gallium (Ga+) ions by focused ion beam (FIB) writing. The defined 3D structures are formed in a final step by selectively wet etching the non-implanted Si in potassium hydroxide (KOH). We demonstrate the viability of the method by fabricating 2 and 3-layer 3D Si structures, including suspended beams and patterned lines with dimensions on the nm-scale.
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| 29. |
- Fischer, Andreas C., 1982-, et al.
(author)
-
Low-Cost Through Silicon Vias (Tsvs) With Wire-Bonded Metal Cores And Low Capacitive Substrate-Coupling
- 2010
-
In: MEMS 2010. - : IEEE. - 9781424457649 ; , s. 480-483
-
Conference paper (peer-reviewed)abstract
- The three-dimensional (3D) integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies using through silicon vias (TSVs). They enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs. This paper presents a novel low-cost fabrication technique for metal-filled TSVs using bonded gold-wires as conductive path. In this concept the wires are surrounded by polymer, which acts both as an electrical insulator causing low capacitive coupling towards the substrate and as a buffer for thermo-mechanical stress.
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| 30. |
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