1. |
- Briand, D., et al.
(author)
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Thermally isolated MOSFET for gas sending application
- 2001
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 22:1, s. 11-13
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Journal article (peer-reviewed)abstract
- This work reports on thermally isolated electronic components for gas sensing applications. The device is composed of an array of 4 MOSFET, a diode and a semiconductor resistor integrated on a micro-hotplate, which is fabricated using bulk micromachining of silicon. The thermal efficiency of the device is 2°C/mW with a thermal constant less than 100 ms. Holes are made in the passivation film over the gates of the MOSFET and gas sensitive films deposited on top of the gate insulator. The low thermal mass device realized allows new modes of operation for MOSFET gas sensors such as a combination of the field and thermal effects and a pulsed temperature mode of operation.
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2. |
- Dillner, Lars, 1968, et al.
(author)
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Frequency Multiplier Measurements on Heterostructure Barrier Varactors on a Copper Substrate
- 2000
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 21:5, s. 206-208
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Journal article (peer-reviewed)abstract
- We have fabricated heterostructure barrier varactors (HBV) on a copper substrate, which offers reduced spreading resistance, and improved thermal conductivity compared to an InP substrate. The devices are fabricated without degrading the electrical characteristics. The three-barrier HBV material grown by MOVPE has a leakage current of only 0.1 mu A/ mu m/sup 2/ at 19 V. The maximum capacitance is 0.54 fF/ mu m/sup 2/. In a frequency tripler experiment a maximum output power of 7.1 mW was generated at 221 GHz with a flange-to-flange efficiency of 7.9%.
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3. |
- Ingvarson, Mattias, 1974, et al.
(author)
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Thermal constraints for heterostructure barrier varactors
- 2004
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In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 25:11, s. 713-715
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Journal article (peer-reviewed)abstract
- Current research on heterostructure barrier varactors (HBVs) devotes much effort to the generation of very high power levels in the millimeter wave region. One way of increasing the power handling capacity of HBVs is to stack several barriers epitaxially. However, the small device dimensions lead to very high temperatures in the active layers, deteriorating the performance. We have derived analytical expressions and combined those with finite element simulations, and used the results to predict the maximum effective number of barriers for HBVs. The thermal model is also used to compare the peak temperature and power handling capacity of GaAs and InP-based HBVs. It is argued that InP-based devices may be inappropriate for high-power applications due to the poor thermal conductivity of the InGaAs modulation layers.
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4. |
- Malm, B. Gunnar, et al.
(author)
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Ge-profile design for improved linearity of SiGe double HBTs
- 2002
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 23:1, s. 19-21
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Journal article (peer-reviewed)abstract
- The influence of Ge-profile design on SiGe HBT linearity-harmonic distortion has been quantified using finite element physical device simulation. It was demonstrated that proper Ge-profile tailoring allows the linearity to be improved for both low- and high-current operation. High injection heterojunction barrier effects are shown to have a significant influence on the higher order harmonies. The influence of the Ge-profile design on linearity was found to be comparable to the influence from the epitaxial collector doping profile.
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7. |
- Sanden, M., et al.
(author)
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Modeling the variation of the low-frequency noise in polysilicon emitter bipolar junction transistors
- 2001
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 22:5, s. 242-244
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Journal article (peer-reviewed)abstract
- The variation of the low-frequency noise in polysilicon emitter bipolar junction transistors (BJTs) was investigated as a function of emitter area (A(E)) For individual BJTs with submicron-sized As, the low-frequency noise strongly deviated from a 1/f-dependence. The averaged noise varied as 1/f, with a magnitude proportional to A(E)(-1), while the variation in the noise level was found to vary as A(E)(-1.5). A new expression that takes into account this deviation is proposed for SPICE modeling of the the low-frequency noise, The traps responsible for the noise were located to the thin SiO2 interface between the polysilicon and monosilicon emitter, The trap's energy level, areal concentration and capture cross-section were estimated to 0.31 eV, 6 x 10(8) cm(-2) and 2 x 10(-19) cm(2), respectively.
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8. |
- See, P., et al.
(author)
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High performance Si/Si1-x Gex resonant tunneling diodes
- 2001
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 22:4, s. 182-184
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Journal article (peer-reviewed)abstract
- Resonant tunneling diodes (RTDs) with strained i-Si0.4 Ge06. potential barriers and a strained i-Si quantum well, all on a relaxed Si0.8 Ge0.2 virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm2 at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si1-x Gex RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si1-x Gex heterojunction field effect transistor based integrated circuits.
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9. |
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10. |
- Willen, Bo G., et al.
(author)
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Experimental evaluation of the InP-InGaAs-HBT power-gain resonance
- 2002
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 23:10, s. 579-581
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Journal article (peer-reviewed)abstract
- An InP-InGaAs HBT has been evaluated that exhibits resonant hole modulation effects at a sufficiently low frequency for the resonance to be completely characterized by network analyzer measurements. It is shown that the frequency dependence of both the unilateral power gain and the current gain are modified by this effect, thus affecting the associated cutoff frequencies f(max) and f(T). A new power gain expression G(P) based on measured small-signal parameters is introduced to circumvent the ambiguity in the unilateral power gain. Finding f(max) and f(T) by means of extrapolation of G(P) and h(21), respectively, from a region below the,resonance frequency is proposed to yield appropriate estimates of the figures-of-merit for device applications.
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11. |
- Willen, Bo G., et al.
(author)
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Unilateral power gain limitations due to dynamic base widening effects
- 2001
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 22:8, s. 370-372
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Journal article (peer-reviewed)abstract
- It is shown that the maximum frequency of oscillation of an InP-HBT may be limited by the low velocity of the holes when operated in the base push-out regime since modulation of the extended base will be delayed by the hole transit time, having an effect also on the electron current. The resulting delay of the current response causes a peaking of the unilateral power gain followed by a -40 dB/decade roll-off, being a source for a strong overestimation of the extrapolated cut-off frequency when neglected,An extended equivalent small-signal circuit is proposed that takes these effects into account.
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12. |
- Wu, D., et al.
(author)
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A novel strained Si0.7Ge0.3 surface-channel pMOSFET with an ALD TiN/Al2O3/HfAlOx/Al2O3 gate stack
- 2003
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 24:3, s. 171-173
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Journal article (peer-reviewed)abstract
- Proof-of-concept pMOSFETs with a strained-Si0.7Ge0.3 surface-channel deposited by selective epitaxy and a TiN/Al2O3/HfAIO(x)/Al2O3 gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si0.7Ge0.3 pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3x10(11) cm(-2) eV(-1), yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si0.7Ge0.3 pMOSFETs, these values were 1.6x10(12) cm(-2) eV(-1) and 110 mV/dec., respectively.
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14. |
- Wu, Donping, et al.
(author)
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Influence of surface treatment prior to ALD high-kappa dielectrics on the performance of SiGe surface-channel pMOSFETs
- 2004
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 25:5, s. 289-291
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Journal article (peer-reviewed)abstract
- Compressively strained Si0.7Ge0.3 surface-channel pMOSFETs with atomic layer deposition (ALD) Al2O3/HfO2/Al2O3 nanolaminate and low-pressure chemical vapor deposition p(+) poly-SiGe gate electrode were fabricated. Surface treatment with either hydrogen fluoride (HF) clean, or HF clean followed by water rinse was performed prior to the ALD processing. The devices with water rinse show a good control of interfacial layer and device reproducibility, while the devices without water rinse lack a clearly observable interfacial layer and show scattered electrical characteristics and distorted mobility curve. A similar to20% increase in hole mobility compared to the Si universal mobility and a similar to0.6-nm-thick continuous interfacial layer are obtained for the pMOSFETs with water rinse.
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15. |
- Lind, Erik, et al.
(author)
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Resonant tunneling permeable base transistors with high transconductance
- 2004
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In: IEEE Electron Device Letters. - 0741-3106. ; 25:10, s. 678-680
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Journal article (peer-reviewed)abstract
- A GaAs-based resonant tunneling permeable base transistor has been developed and evaluated at room temperature. The transistor is fabricated by overgrowing a tungsten gate placed next to an AlGaAs-GaAs-InGaAs resonant tunneling heterostructure. By changing the gate voltage, the effective conducting area of the tunnel diode can be modulated and the collector-emitter current thus controlled. Peak currents above 300 mA/mm and a maximum transconductance of 270 mS/mm have been obtained.
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16. |
- Shorubalko, Ivan, et al.
(author)
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A novel frequency-multiplication device based on three-terminal ballistic junction
- 2002
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In: IEEE Electron Device Letters. - 0741-3106. ; 23:7, s. 377-379
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Journal article (peer-reviewed)abstract
- In this letter, a novel frequency-multiplication device based on a three-terminal ballistic junction is proposed and demonstrated. A 100 nm-size, three-terminal ballistic junction and a one-dimensional (1-D), lateral-field-effect transistor with trench gate-channel insulation are fabricated from high-electron-mobility GaInAs/InP quantum-well material as a single device. The devices show frequency doubling and gain at room temperature. The performance of these devices up to room temperature originates from the nature of the device functionality and the fact that the three-terminal device extensions are maintained below the carrier mean-free path. Furthermore, it is expected that the device performance can be extended up to THz-range.
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17. |
- Xu, Hongqi, et al.
(author)
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Novel nanoelectronic triodes and logic devices with TBJs
- 2004
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In: IEEE Electron Device Letters. - 0741-3106. ; 25:4, s. 164-166
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Journal article (peer-reviewed)abstract
- In this letter, we demonstrate the realization of novel diodes, triodes, and logic gates with three-terminal ballistic junctions (TBJs) made from a semiconductor heterostructure. The approach exploits the ballistic nature of electron transport, which has emerged in the nanostructures. Importantly, we show that TBJs function as logic AND gates and can be used to construct other compound logic gates, such as NAND gates with voltage gain, when combined with a point contact (an inverter). The demonstrated devices show favorable characteristics such as low turn-on voltage in rectification and room-temperature operation.
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