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1.	Bonmann, Marlene, 1988, et al. (author) Graphene field-effect transistors with high extrinsic fT and fmax 2019 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 40:1, s. 131-134 Journal article (peer-reviewed)abstract In this work, we report on the performance of graphene field-effect transistors (GFETs) in which the extrinsic transit frequency (fT) and maximum frequency of oscillation (fmax) showed improved scaling behavior with respect to the gate length (Lg). This improvement was achieved by the use of high-quality graphene in combination with successful optimization of the GFET technology, where extreme low source/drain contact resistances were obtained together with reduced parasitic pad capacitances. GFETs with gate lengths ranging from 0.5 μm to 2 μm have been characterized, and extrinsic fT and fmax frequencies of up to 34 GHz and 37 GHz, respectively, were obtained for GFETs with the shortest gate lengths. Simulations based on a small-signal equivalent circuit model are in good agreement with the measured data. Extrapolation predicts extrinsic fT and fmax values of approximately 100 GHz at Lg=50 nm. Further optimization of the GFET technology enables fmax values above 100 GHz, which is suitable for many millimeter wave applications.
2.	Borg, Johan (author) Performance and spatial sensitivity variations of single photon avalanche diodes manufactured in an image sensor CMOS process 2015 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 36:11, s. 1118-1120 Journal article (peer-reviewed)abstract In this letter we present the results from a series of single-photon avalanche diode (SPAD) structures implemented in a commercial 0.18 μm CMOS process intended for CMOS image sensors. Variations without effect on the performance and variations that produced non-functional devices are described. Devices based on the P+/NWELL and deep-NWELL/P-EPI SPADs junctions were found to work well in this process. When biased for 10% QE the best 10 μm diameter P+/NWELL SPADs exhibited a DCR of about 1 kHz, whereas the DCR of the deep-NWELL/P-EPI SPADs was only 10 Hz under the same conditions. We also show that the former type exhibited local sensitivity variations within the SPADs ranging from a factor 4 at low excess voltage to 1.2 at an excess voltage of about 0.5 V. No significant sensitivity variations were found for the deep- NWELL/P-EPI SPADs, but they were found to exhibit significant sensitivity outside the central junction, contributing from 8.3 % at low excess voltage to approximately 70% at high excess voltage
3.	Dong, Y. B., et al. (author) High Light Extraction Efficiency AlGaInP LEDs With Proton Implanted Current Blocking Layer 2016 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 37:10, s. 1303-1306 Journal article (peer-reviewed)abstract Improving light extraction efficiency is the key issue for light-emitting diodes (LEDs). Nowadays, a vertical structure design dominates LEDs. However, the light from the active region just below the p-electrode is severely blocked by the metal contact. In this letter, we use proton implantation with a depth all the way to the active region to turn the part beneath the p-pad insulating, which constitutes the most-effective-ever current blocking method. Earlier particle implantation studies never reached the device active region. Our experimental results show that the H+-implanted LEDs improve the light output power by 75% compared with non-implanted counterparts and the light intensity increases by 64.48%. By virtue of indium tin oxide current spreading film, the increase in working voltage is negligible. Analyzing the reverse leakage current, the side effect associated with the implantation is limited to an acceptable range. Numerical simulation is performed to support the experiment. Our results represent a new and simple method for solving the light blocking problem in vertical LEDs, without introducing the seemingly existing severe implantation damage to the device structure.
4.	Ekström, Mattias, 1990-, et al. (author) High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators 2019 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 40:5, s. 670-673 Journal article (peer-reviewed)abstract Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.
5.	Elahipanah, Hossein, et al. (author) 5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension 2015 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 36:2, s. 168-170 Journal article (peer-reviewed)abstract Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.
6.	Elahipanah, Hossein, 1982-, et al. (author) 500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits 2017 In: IEEE Electron Device Letters. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0741-3106 .- 1558-0563. Journal article (peer-reviewed)abstract High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.
7.	Habibpour, Omid, 1979, et al. (author) Graphene FET Gigabit On-Off Keying Demodulator at 96 GHz 2016 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 37:3, s. 333-336 Journal article (peer-reviewed)abstract We demonstrate the demodulation of a multi-Gb/s ON-OFF keying (OOK) signal on a 96 GHz carrier by utilizing a 250-nm graphene field-effect transistor as a zero bias power detector. From the eye diagram, we can conclude that the devices can demodulate the OOK signals up to 4 Gb/s.
8.	Hedayati, Raheleh, et al. (author) Wide Temperature Range Integrated Bandgap Voltage References in 4H–SiC 2016 In: IEEE Electron Device Letters. - : IEEE. - 0741-3106 .- 1558-0563. ; 37:2, s. 146-149 Journal article (peer-reviewed)abstract Three fully integrated bandgap voltage references (BGVRs) have been demonstrated in a 4H-SiC bipolar technology. The circuits have been characterized over a wide temperature range from 25 degrees C to 500 degrees C. The three BGVRs are functional and exhibit 46 ppm/degrees C, 131 ppm/degrees C, and 120 ppm/degrees C output voltage variations from 25 degrees C up to 500 degrees C. This letter shows that SiC bipolar BGVRs are capable of providing stable voltage references over a wide temperature range.
9.	Hou, Shuoben, et al. (author) 550 degrees C 4H-SiC p-i-n Photodiode Array With Two-Layer Metallization 2016 In: IEEE Electron Device Letters. - : IEEE. - 0741-3106 .- 1558-0563. ; 37:12, s. 1594-1596 Journal article (peer-reviewed)abstract The p-i-n ultraviolet (UV) photodiodes based on 4H-SiC have been fabricated and characterized from room temperature (RT) to 550 degrees C. Due to bandgap narrowing at higher temperatures, the photocurrent of the photodiode increases by 9 times at 365 nm and reduces by 2.6 times at 275 nm from RT to 550 degrees C. Moreover, a 4H-SiC p-i-n photodiode array has been fabricated. Each column and row of the array is separately connected by two-layer metallization.
10.	Hou, Shuoben, et al. (author) A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode 2019 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 40:1, s. 51-54 Journal article (peer-reviewed)abstract This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.
11.	Huang, Tongde, 1985, et al. (author) Achieving Low-Recovery Time in AlGaN/GaN HEMTs With AlN Interlayer Under Low-Noise Amplifiers Operation 2017 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 38:7, s. 926-928 Journal article (peer-reviewed)abstract Three transistors with different AlGaN/GaN interface designs (sharp interface, standard interface, and an extra AlN interlayer) were studied in-depth under conditions mimicking low-noise amplifiers (LNAs) operation. A new measurement setup, analog to LNAs operation condition, is established to measure recovery time on device level. For the first time, a direct relationship between the recovery time and the design of AlGaN/GaN interface is revealed in devices with Carbon doping buffer in this letter. An extremely low-recovery time is demonstrated in the transistor with an AlN interlayer. Both transistors without an AlN interlayer exhibit severe gain and drain current degradation after pulsed input stress. The transistor with a sharp interface shows a recovery time around 10 ms, whereas the transistor with a standard interface shows even much longer recovery time. These results imply that AlN interlayer, which can effectively block the injection of hot electrons to AlGaN bulk or surface traps, is highly preferred in systems where LNAs need to function promptly after an input overdrive.
12.	Huang, Tongde, 1985, et al. (author) Suppression of Dispersive Effects in AlGaN/GaN High-Electron-Mobility Transistors Using Bilayer SiNx Grown by Low Pressure Chemical Vapor Deposition 2015 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 36:6, s. 537-539 Journal article (peer-reviewed)abstract A bilayer SiNx passivation scheme has been developed using low pressure chemical vapor deposition (LPCVD), which effectively suppresses the dispersive effects in AlGaN/GaN high-electron-mobility transistors (HEMTs) for microwave power operation. The bilayer LPCVD passivation is compared with in-situ SiNx passivations by metal-organic chemical vapor deposition (MOCVD) and ex-situ SiNx passivations by plasma-enhanced chemical vapor deposition (PECVD). The HEMTs were fabricated and characterized in terms of pulsed IV, transient drain current, and load pull. The devices passivated with in-situ MOCVD SiNx or PECVD SiNx exhibit significant current slump (similar to 40%) and knee-voltage walkout, while the bilayer LPCVD SiNx passivated device shows negligible current slump (similar to 6%) and knee-voltage walkout. These characteristics are directly reflected in the large signal operation, where HEMTs with bilayer LPCVD SiNx have the lowest dynamic ON-state resistance and highest output power (5.4 W/mm at 3 GHz).
13.	Hussain, Muhammad Waqar, 1985-, et al. (author) A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology 2018 In: IEEE Electron Device Letters. - : IEEE Press. - 0741-3106 .- 1558-0563. ; 39:6, s. 855-858 Journal article (peer-reviewed)abstract This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.
14.	Jiang, Di, 1983, et al. (author) Vertically stacked carbon nanotube-based interconnects for through silicon via application 2015 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 36:5, s. 499-501 Journal article (peer-reviewed)abstract Stacking of silicon chips with carbon nanotube (CNT)-based through-silicon vias (TSVs) is experimentally demonstrated. Polymer filling is used to improve the transfer quality of CNTs into pre-etched silicon holes. Special hexagonal CNTs are designed to achieve high aspect ratio (10:1) CNT vias. TSVs filled with closely packed CNTs show a highly linear dc I - V response. The proposed process works at room temperature, which makes it compatible with existing device fabrication flow.
15.	Kargarrazi, S., et al. (author) 500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology 2018 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 39:4, s. 548-551 Journal article (peer-reviewed)abstract This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).
16.	Kovi, Kiran Kumar, 1980-, et al. (author) Inversion in Metal–Oxide–Semiconductor Capacitors on Boron-Doped Diamond 2015 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 36:6, s. 603-605 Journal article (peer-reviewed)abstract For the advancement of diamond-based electronic devices, the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial, as this device finds applications in numerous fields of power electronics and high-frequency systems. The MOS capacitor forms the basic building block of the MOSFET. In this letter, we describe planar MOS capacitor structures fabricated with atomic layer deposited aluminum oxide as the dielectric on oxygen-terminated boron-doped diamond substrates with different doping levels. Using capacitance-voltage measurements, we have, for the first time, observed inversion behavior in MOS structures on boron-doped diamond, with a doping concentration of 4.1 × 1019/cm3.
17.	Lanni, Luigia, et al. (author) Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs 2015 In: IEEE Electron Device Letters. - : IEEE Press. - 0741-3106 .- 1558-0563. ; 36:1, s. 11-13 Journal article (peer-reviewed)abstract The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50-150 nm were deposited prior to the same annealing process in N2O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, similar to 60% higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of similar to 200 at room temperature and >100 at 300 degrees C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains.
18.	Lin, Min-Zhi, et al. (author) A High-Speed Si-Based Power Transistor With Bipolar-Assisted Gate Discharging Behavior 2019 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 40:4, s. 589-592 Journal article (peer-reviewed)
19.	Malmros, Anna, 1977, et al. (author) Evaluation of Thermal Versus Plasma-Assisted ALD Al2O3 as Passivation for InAlN/AlN/GaN HEMTs 2015 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 36:3, s. 235-237 Journal article (peer-reviewed)abstract Al2O3 films deposited by thermal and plasma-assisted atomic layer deposition (ALD) were evaluated as passivation layers for InAlN/AlN/GaN HEMTs. As a reference, a comparison was made with the more conventional plasma enhanced chemical vapor deposition deposited SiNx passivation. The difference in sheet charge density, threshold voltage, f(T) and f(max) was moderate for the three samples. The gate leakage current differed by several orders of magnitude, in favor of Al2O3 passivation, regardless of the deposition method. Severe current slump was measured for the HEMT passivated by thermal ALD, whereas near-dispersion free operation was observed for the HEMT passivated by plasma-assisted ALD. This had a direct impact on the microwave output power. Large-signal measurements at 3 GHz revealed that HEMTs with Al2O3 passivation exhibited 77% higher output power using plasma-assisted ALD compared with thermal ALD.
20.	Olyaei, Maryam, et al. (author) Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs 2015 In: IEEE Electron Device Letters. - : IEEE Press. - 0741-3106 .- 1558-0563. ; 36:12, s. 1355-1358 Journal article (peer-reviewed)abstract Low-frequency noise measurements were performed on n-channel MOSFETs with a novel ultra-low 0.3nm EOT interfacial layer (TmSiO) and two different bulk high-k dielectrics (Tm2O3 and HfO2). The MOSFETs were fabricated in a gate-last process and the total gate stack EOT was 1.2 nm and 0.65 nm for the Tm2O3 and HfO2 samples respectively. In general both gate stacks resulted in 1/f type of noise spectra and noise levels comparable to conventional SiO2/HfO2 devices with similar EOTs. The extracted average effective oxide trap density was 2.5×1017 cm-3eV-1 and 1.5×1017 cm-3eV-1 for TmSiO/HfO2 and TmSiO/Tm2O3 respectively. Therefore the best noise performance was observed for the gate stack with Tm2O3 bulk high-k layer and we suggest that the interface free single layer ALD fabrication scheme could explain this.
21.	Pan, G. Z., et al. (author) Large-Scale Proton-Implant-Defined VCSEL Arrays with Narrow Beamwidth 2018 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 39:3, s. 390-393 Journal article (peer-reviewed)abstract In-phase coherently coupled proton-implant-defined vertical cavity surface emitting laser (VCSEL) arrays face difficulties in current spreading, resulting in small array scale, low output power, and broad beamwidth. Although patterned metal grids can improve the current spreading, the undesirable out-of-phase mode tends to be dominant in the array. In this letter, by means of engineering the implantation and array parameters, in-phase mode is obtained in large-scale proton-implant-defined arrays with metal grids. Experimental results show that these arrays are operating in in-phase mode with a nominal interelement spacing of 8 μm and an implantation depth of 2.22 μm. By using these parameters, a 5 × 5 in-phase array with a narrow beamwidth (far-field full width at half maximum) of 1.61° is realized. Besides, a 10 × 10 in-phase array with a beamwidth of 1.89° and an output power of 10.25 mW for the in-phase mode is achieved. The calculation of far fields is performed to confirm the in-phase operation measured results. Such a simple and low-cost technology provides a promising method for preparing large-scale in-phase coherently coupled VCSEL arrays.
22.	Salemi, Arash, et al. (author) 15 kV-Class implantation-Free 4H-SiC BJTs with Record High Current Gain 2016 In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. Journal article (other academic/artistic)abstract Implantation-free mesa-etched ultra-high-voltage 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension (O-JTE) is utilized in order to obtain a high and stable breakdown voltage without ion implantation. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared. The base size effect is investigated in order to improve current gain.
23.	Salemi, Arash, et al. (author) 15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain 2018 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 39:1, s. 63-66 Journal article (peer-reviewed)abstract Implantation-free mesa-etched ultra-high-voltage (0.08 mm(2)) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm(2) is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.
24.	Salemi, Arash, et al. (author) Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs 2015 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 36:10, s. 1069-1072 Journal article (peer-reviewed)abstract Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (R-ON), current density (J(C)), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.
25.	Shakir, Muhammad, et al. (author) A 600 degrees C TTL-Based 11-Stage Ring Oscillator in Bipolar Silicon Carbide Technology 2018 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 39:10, s. 1540-1543 Journal article (peer-reviewed)abstract Ring oscillators (ROs) are used to study the high-temperature characteristics of an in-house silicon carbide (SiC) technology. Design and successful operation of the in-house-fabricated 4H-SiC n-p-n bipolar transistors and TTL inverter-based 11-stage RO are reported from 25 degrees C to 600 degrees C. Non-monotonous temperature dependence was observed for the oscillator frequency; in the range of 25 degrees C to 300 degrees C, it increased with the temperature (1.33 MHz at 300 degrees C and V-CC = 15 V), while it decreased in the range of 300 degrees C-600 degrees C. The oscillator output frequency and delay were also characterized over a wide range of supply voltage (10 to 20 V). The noise margins of the TTL inverter were also measured; noise margin low (NML) decreases with the temperature, whereas noise margin high (NMH) increases with the temperature. The measured power-delay product (P-D . T-P) of the TTL inverter and 11-stage RO was approximate to 4.5 and approximate to 285 nJ, respectively, at V-CC= 15 V. Reliability testing indicated that the RO frequency of oscillation decreased 16% after HT characterization.

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