1. |
- Lohstroh, M., et al.
(author)
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Invited : Actors revisited for time-critical systems
- 2019
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In: Proceedings - Design Automation Conference. - New York, NY, USA : Institute of Electrical and Electronics Engineers Inc.. - 9781450367257
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Conference paper (peer-reviewed)abstract
- Programming time-critical systems is notoriously difficult. In this paper we propose an actor-oriented programming model with a semantic notion of time and a deterministic coordination semantics based on discrete events to exercise precise control over both the computational and timing aspects of the system behavior.
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2. |
- Falk, H., et al.
(author)
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TACLeBench : A benchmark collection to support worst-case execution time research
- 2016
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In: OpenAccess Series in Informatics. - 9783959770255 ; , s. 2.1-2.10
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Conference paper (peer-reviewed)abstract
- Engineering related research, such as research on worst-case execution time, uses experimentation to evaluate ideas. For these experiments we need example programs. Furthermore, to make the research experimentation repeatable those programs shall be made publicly available. We collected open-source programs, adapted them to a common coding style, and provide the collection in open-source. The benchmark collection is called TACLeBench and is available from GitHub in version 1.9 at the publication date of this paper. One of the main features of TACLeBench is that all programs are self-contained without any dependencies on standard libraries or an operating system.
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3. |
- Gruian, Flavius, et al.
(author)
-
Automatic generation of application-specific systems based on a micro-programmed Java core
- 2005
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In: Proceedings of the ACM Symposium on Applied Computing. - New York, NY, USA : ACM. ; 1, s. 879-884
-
Conference paper (peer-reviewed)abstract
- This paper describes a co-design based approach for automatic generation of application specific systems, suitable for FPGA-centric embedded applications. The approach augments a processor core with hardware accelerators extracted automatically from a high-level specification (Java) of the application, to obtain a custom system, optimised for the target application. We advocate herein the use of a micro-programmed core as the basis for system generation in order to hide the hardware access operations in the micro-code, while conserving the core data-path (and clock frequency). To prove the feasibility of our approach, we also present an implementation based on a modified version of the Java Optimized Processor soft core on a Xilinx Virtex-II FPGA. Copyright 2005 ACM.
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