| 1. |
- Elahipanah, Hossein, et al.
(author)
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4.5-kV 20-mΩ. cm2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension
- 2015
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In: Materials Science Forum. - : Trans Tech Publications Ltd. - 0255-5476 .- 1662-9752. - 9783038354789 ; 821, s. 838-841
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Journal article (peer-reviewed)abstract
- A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.
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| 2. |
- Elahipanah, Hossein, et al.
(author)
-
5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension
- 2015
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 36:2, s. 168-170
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Journal article (peer-reviewed)abstract
- Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.
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| 3. |
- Salemi, Arash, et al.
(author)
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Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance
- 2015
-
In: 2015 IEEE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD). - : IEEE. - 9781479962617 ; , s. 249-252
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Conference paper (peer-reviewed)abstract
- Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of beta = 44 at a current density of 472 A/cm(2), and a specific on-resistance of R-ON = 18.8 m Omega.cm(2) is obtained for the device. The device shows a negative temperature coefficient of the current gain (beta = 14.5 at 200 degrees C) and a positive temperature coefficient of on-resistance (R-ON = 57.3 m Omega.cm(2) at 200 degrees C).
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| 4. |
- Salemi, Arash, et al.
(author)
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Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes
- 2015
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In: Proceedings of the International Symposium on Power Semiconductor Devices and ICs. - : IEEE conference proceedings. - 9781479962594 - 9781479962617 ; , s. 269-272
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Conference paper (peer-reviewed)abstract
- Degradation-free ultrahigh-voltage (>10 kV) PiN diodes using on-axis 4H-SiC with low forward voltage drop (VF = 3.3 V at 100 A/cm2) and low differential on-resistance (RON = 3.4 m.cm2) are fabricated, measured, and analyzed by device simulation. The devices show stable on-state characteristics over a broad temperature range up to 300 °C. They show no breakdown up to 10 kV, i.e., the highest blocking capability for 4H-SiC devices using on-axis to date. The minority carrier lifetime (τP) is measured after epitaxial growth by time resolved photoluminescence (TRPL) technique at room temperature. The τP is measured again after device fabrication by open circuit voltage decay (OCVD) up to 500 K.
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| 5. |
- Salemi, Arash, et al.
(author)
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Investigation of the breakdown voltage in high voltage 4H-SiC BJT with respect to oxide and interface charges
- 2015
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In: Materials Science Forum. - : Trans Tech Publications Inc.. - 0255-5476 .- 1662-9752. - 9783038354789 ; 821-823, s. 834-837
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Journal article (peer-reviewed)abstract
- Ion implantation in silicon carbide (SiC) induces defects during the process. Implantation free processing can eliminate these problems. The junction termination extension (JTE) can also be formed without ion implantation in SiC bipolar junction transistor (BJT) using a well-controlled etching into the epitaxial base layer. The fixed charges at the SiC/SiO2 interface modify the effective dose of the JTEs, leakage current, and breakdown voltage. In this paper the influence of fixed charges (positive and negative) and also interface trap density at the SiC/SiO2 interface on the breakdown voltage in 4.5 kV 4H-SiC non-ion implanted BJT have been simulated. SiO2 as a surface passivation layer including interface traps and fixed charges has been considered in the analysis. Simulation result shows that the fixed charges influence the breakdown voltage significantly more than the interface traps. It also shows that the positive fixed charges reduce the breakdown voltage more than the negative fixed charges. The combination of interface traps and fixed charges must be considered when optimizing the breakdown voltage.
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| 6. |
- Salemi, Arash, et al.
(author)
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Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs
- 2015
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In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 36:10, s. 1069-1072
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Journal article (peer-reviewed)abstract
- Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (R-ON), current density (J(C)), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.
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