| 1. |
- Kamuf, Matthias, et al.
(author)
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A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
- 2008
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In: Proceedings, Norchip Conference. ; , s. 137-141
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Conference paper (peer-reviewed)abstract
- This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
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| 2. |
- Kamuf, Matthias, et al.
(author)
-
Optimization and implementation of a Viterbi decoder under flexibility constraints
- 2008
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In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 55:8, s. 2411-2422
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Journal article (peer-reviewed)abstract
- This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13- $mu{hbox {m}}$ CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.
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| 3. |
- Rupanagudi, Sudhir Rao, et al.
(author)
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Reducing computational complexity of branch metric calculations in a trellis decoder
- 2008
-
Conference paper (peer-reviewed)abstract
- Trellis decoding is widely used, in this present day of communication and data storage, in a wide variety of applications such as decoding convolution codes, baseband detection for wireless systems and also to detect recorded data. This is achieved by implementing the Viterbi algorithm. This paper presents various methodologies of reducing the computational complexity of the branch metric unit in a trellis decoder. Further, a new methodology identified by us, which can be used to simplify the computations further, has been discussed. The adoption of this method, has been verified in a 0.13μ standard CMOS process, which shows 60% reduction in area as compared to the designs incorporating the existing methodologies.
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