| 1. |
- Abermann, S., et al.
(author)
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Comparative study on the impact of TiN and Mo metal gates on MOCVD-grown HfO2 and ZrO2 high-kappa dielectrics for CMOS technology
- 2007
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In: Physics of Semiconductors, Pts A and B. - : AIP. - 9780735403970 ; , s. 293-294
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Conference paper (peer-reviewed)abstract
- We compare metal oxide semiconductor capacitors, investigating Titanium-Nitride and Molybdenum as gate materials, as well as metal organic chemical vapor deposited ZrO2 and HfO2 as high-kappa dielectrics, respectively. The impact of different annealing steps on the electrical characteristics of the various gate stacks is a further issue. The positive effect of post metallization annealing in forming gas atmosphere as well as observed mid-gap pinning of TiN and Mo metal gates is presented.
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| 2. |
- Abermann, S., et al.
(author)
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Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown HfO2 and ZrO2 high-k dielectrics
- 2007
-
In: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:4-5, s. 536-539
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Journal article (peer-reviewed)abstract
- In this work we compare the impacts of nickel (Ni), titanium-nitride (TiN), molybdenum (Mo), and aluminium (Al), gates on MOS capacitors incorporating HfO2- or ZrO2-dielectrics. The primary focus lies on interface trapping, oxide charging, and thermodynamical stability during different annealing steps of these gate stacks. Whereas Ni, Mo, and especially TIN are investigated as most promising candidates for future CMOS devices, Al acted as reference gate material to benchmark the parameters. Post-metallization annealing of both, TiN- and Mo-stacks, resulted in very promising electrical characteristics. However, gate stacks annealed at temperatures of 800 degrees C or 950 degrees C show thermodynamic instability and related undesirable high leakage currents.
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| 3. |
- Abermann, S., et al.
(author)
-
Processing and evaluation of metal gate/high-kappa/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-kappa dielectric
- 2007
-
In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638
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Journal article (peer-reviewed)abstract
- We evaluate various metal gate/high-K/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
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| 4. |
- Buiu, O., et al.
(author)
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Extracting the relative dielectric constant for "high-k layers" from CV measurements : Errors and error propagation
- 2007
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In: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:4-5, s. 678-681
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Journal article (peer-reviewed)abstract
- The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., kappa value) from capacitance-voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-rc dielectric and the silicon substrate is a factor that affects - in general - the assessment of the electrical data, as well as the extraction of rc. A methodology which accounts for this transition layer and the errors related to other parameters involved in the k value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO2/SiOx/Si structures produced in different conditions.
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| 5. |
- Driussi, F., et al.
(author)
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Fabrication, characterization and modeling of strained SOI MOSFETs with very large effective mobility
- 2007
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In: ESSDERC 2007. - 9781424411238 ; , s. 315-318
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Conference paper (peer-reviewed)abstract
- Strained Silicon on insulators (sSOI) wafers with a supercritical thickness of 58 nm were produced using thin strain relaxed SiGe buffer layers, wafer bonding, selective etch back and epitaxial overgrowth. Raman spectroscopy revealed an homogeneous strain of 0.63 +/- 0.03% in the strained Si layer. Long channel n-type SOI-MOSFETs showed very large electron mobilities up to 1200 cm(2)/Vs in the strained Si devices. These values are more than two times larger than those of reference SOI n-MOSFETs. Mobility simulations with state of the art scattering models are then used to interpret the experiments.
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| 6. |
- Echtermeyer, T., et al.
(author)
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Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes
- 2007
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In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 617-621
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Journal article (peer-reviewed)abstract
- Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.
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| 7. |
- Echtermeyer, T. J., et al.
(author)
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Graphene field-effect devices
- 2007
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In: The European Physical Journal Special Topics. - : Springer Science and Business Media LLC. - 1951-6355 .- 1951-6401. ; 148:1, s. 19-26
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Journal article (peer-reviewed)abstract
- In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices ( FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors ( MOSFETs).
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| 8. |
- Engstrom, O., et al.
(author)
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Navigation aids in the search for future high-k dielectrics : Physical and electrical trends
- 2007
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In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 622-626
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Journal article (peer-reviewed)abstract
- From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.
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| 9. |
- Lemme, Max C., 1970-, et al.
(author)
-
A graphene field-effect device
- 2007
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In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 28:4, s. 282-284
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Journal article (peer-reviewed)abstract
- In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs.
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| 10. |
- Lemme, Max C., 1970-, et al.
(author)
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Non-planar devices for nanoscale CMOS
- 2007
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In: Nanoscaled Semiconductor-on-Insulator Structures and Devices. - Dordrecht : Springer Netherlands. - 9781402063787 ; , s. 19-32
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Conference paper (peer-reviewed)abstract
- In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and rnanufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.
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| 11. |
- Nazarov, A. N., et al.
(author)
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Charge trapping in ultrathin Gd2O3 high-k dielectric
- 2007
-
In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:9-10, s. 1968-1971
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Journal article (peer-reviewed)abstract
- Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 x 10(-20) cm(2). The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 x 10(12) eV(-1) cm(-2) near the valence band edge.
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| 12. |
- Passi, Vikram, et al.
(author)
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Suspended silicon-on-insulator nanowires for the fabrication of quadruple gate mosfets
- 2007
-
In: Nanoscaled Semiconductor-on-Insulator Structures and Devices. - Dordrecht : Springer Netherlands. - 9781402063787 ; , s. 89-94
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Conference paper (peer-reviewed)abstract
- Scaling of MOSFET physical dimensions is approaching the OF nanoscale regime, which causes increase of short-channel effects such that the electrical performance of classical MOSFET structure is becoming seriously degraded. The limits of silicon scaling have been the major challenge for technologists for the past years. With the 90 nm generation in production and despite many roadblocks, the latest International Roadmap for Semiconductors 2005 expects that CMOS can be scaled down to 16 nm, by introducing new transistor architectures and materials. In this paper, we propose fabrication of a non-classical device architecture namely the "Quadruple-Gate MOSFET" which is based on definition of narrow, suspended silicon fins defined by electron-beam lithography into the top-silicon film of a Silicon-on-Insulator (SOI) wafer.
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| 13. |
- Raeissi, Bahman, 1979, et al.
(author)
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High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
- 2007
-
In: ESSDERC 2007. - 9781424411238 ; , s. 283-286
-
Conference paper (peer-reviewed)abstract
- Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd(2)O(3) prepared by MBE and ALD, and for HfO(2) prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.
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| 14. |
- Wahlbrink, T., et al.
(author)
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Supercritical drying for high aspect-ratio HSQ nano-structures
- 2007
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1045-1048
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Journal article (peer-reviewed)abstract
- The benefits of supercritical resist drying (SRD) technique using carbon dioxide (CO2) are investigated with respect to the resolution of dense patterns and the aspect ratio (AR) of nano-structures in rather thick HSQ layers. For double lines separated by a distance of 50 nm the maximum achievable AR is trebled using SRD processes compared to conventional nitrogen blow. The mechanical stability of resist structures is significantly improved by using SRI).
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