| 1. |
- Memisevic, E., et al.
(author)
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Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at VDS = 0.3 V
- 2017
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In: 2016 IEEE International Electron Devices Meeting, IEDM 2016. - 9781509039012 ; , s. 1-19
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Conference paper (peer-reviewed)abstract
- We present a vertical nanowire InAs/GaAsSb/GaSb TFET with a highly scaled InAs diameter (20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for Vds = 0.1-0.5 V and achieves an Ion = 10.6 μA/μm for Ioff = 1 nA/μm at Vds = 0.3 V. The lowest subthreshold swing achieved is 44 mV/dec. at Vds= 0.05 V. Furthermore, a benchmarking is performed against state-of-the-art TFETs and MOSFETs demonstrating a record high I60 and performance benefits for Vds between 0.1 and 0.3 V.
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| 2. |
- Larsson, D. G. Joakim, 1969, et al.
(author)
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Critical knowledge gaps and research needs related to the environmental dimensions of antibiotic resistance
- 2018
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In: Environment International. - : Elsevier BV. - 0160-4120 .- 1873-6750. ; 117, s. 132-138
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Research review (peer-reviewed)abstract
- There is growing understanding that the environment plays an important role both in the transmission of antibiotic resistant pathogens and in their evolution. Accordingly, researchers and stakeholders world-wide seek to further explore the mechanisms and drivers involved, quantify risks and identify suitable interventions. There is a clear value in establishing research needs and coordinating efforts within and across nations in order to best tackle this global challenge. At an international workshop in late September 2017, scientists from 14 countries with expertise on the environmental dimensions of antibiotic resistance gathered to define critical knowledge gaps. Four key areas were identified where research is urgently needed: 1) the relative contributions of different sources of antibiotics and antibiotic resistant bacteria into the environment; 2) the role of the environment, and particularly anthropogenic inputs, in the evolution of resistance; 3) the overall human and animal health impacts caused by exposure to environmental resistant bacteria; and 4) the efficacy and feasibility of different technological, social, economic and behavioral interventions to mitigate environmental antibiotic resistance.(1)
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| 3. |
- Memisevic, Elvedin, et al.
(author)
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InAs/GaSb vertical nanowire TFETs on Si for digital and analogue applications
- 2016
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In: 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. - 9781509007264 ; , s. 154-155
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Conference paper (peer-reviewed)abstract
- Vertical InAs/GaSb nanowire TFETs with diameters of 20 nm and 25 nm have been fabricated and characterized. The influence of diameter, gate-placement, and nanowire numbers have been studied. The best device shows a subthreshold swing of 68 mV/dec at VDS = 0.3 V and 26 μA/μm at VDS = 0.3 V and VGS = 0.5 V. It achieves a self-gain larger than 100 with high transconductance efficiency.
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| 4. |
- Rosca, T., et al.
(author)
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An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K
- 2019
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In: 2018 IEEE International Electron Devices Meeting, IEDM 2018. - 9781728119878 ; 2018, s. 1-13
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Conference paper (peer-reviewed)abstract
- In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough to maintain excellent figures of merit over a large temperature range even in devices with a large number arrayed nanowires (here, from 4 to 184 nanowires per device), accounting for technological variability. The investigated Tunnel FETs have temperature-independent min and average subthreshold swings of 45mV/dec/67mV/dec in large NW arrays, versus ∼36/45mV/dec in smaller arrays, once the trap-assisted tunneling is removed (from 150K down to 10K). In all NW arrays we observe improvement of the on-current and of maximum transconductance, gmax, at cryogenic temperatures, with very little dependence of temperature, from 150K to 10K. The paper reports that in the range 150K to 10K only band-to-band-tunneling dominates the analog figures of merit of Tunnel FETs; we measured transconductance efficiencincies higher than 60V -1 for small arrays (breaking the limit of CMOS at RT) and close to 42V -1 for large arrays, for supply volrages smaller than 100mV, offering the possibility to design future energy efficient readouts and analog-to-digital converters. In contrast with cryogenic MOSFETs, Tunnel FETs show almost no hysteresis (<24mV), steep transfer characteristics, are free of kinks in output characteristics, with a unique stability of the swing drift with T, and negligible threshold voltage drift in all arrays configurations.
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| 5. |
- Schenk, A., et al.
(author)
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The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs
- 2017
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In: 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017. - 9784863486102 ; 2017-September, s. 273-276
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Conference paper (peer-reviewed)abstract
- Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter into the volume-inversion regime. Gate alignment steepens the slope and increases the ON-current. The 'trap-tolerant' device geometry can result in a small sub-threshold swing despite commonly present trap concentrations.
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| 6. |
- Vasen, T., et al.
(author)
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InAs nanowire GAA n-MOSFETs with 12-15 nm diameter
- 2016
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In: 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. - 9781509006373 ; 2016-September
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Conference paper (peer-reviewed)abstract
- InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-All-Around (GAA) MOSFETs with d = 12-15 nm are demonstrated. Ion = 314 μA/μm, and Ssat =68 mV/dec was achieved at Vdd = 0.5 V (Ioff = 0.1 μA/μm). Highest gm measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between gm, Ron, and Imin are discussed.
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| 7. |
- Zhang, J., et al.
(author)
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Projected performance of experimental InAs/GaAsSb/GaSb TFET as millimeter-wave detector
- 2018
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In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. - 9781538637654 ; 2018-March, s. 1-2
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Conference paper (peer-reviewed)abstract
- Based on measurements of a vertical nanowire InAs/GaAsSb/GaSb tunneling field-effect transistor (TFET) that exhibited minimum subthreshold swing of 48 mV/dec and a record high I60 of 0.31 μA/μm, a SPICE model has been generated to allow an experimentally-based prediction of the nanowire TFET technology. At 30 GHz the detector has been simulated to reveal a sensitivity of 4.8 kV/W biased near zero volts (VGS =-0.06 V, VDS = 0.1 V). A maximum sensitivity of over 4000 kV/W has been obtained under biased conditions. These results exceed prior measurements of an In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction TFET by over an order of magnitude.
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| 8. |
- Zota, C. B., et al.
(author)
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High-frequency InGaAs tri-gate MOSFETs with fmax of 400 GHz
- 2016
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In: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 52:22, s. 1869-1871
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Journal article (peer-reviewed)abstract
- Extremely scaled down tri-gate RF metal-oxide-semiconductor field-effect transistors (MOSFETs) utilising lateral nanowires as the channel, with gate length and nanowire width both of 20 nm are reported. These devices exhibit simultaneous extrapolated ft and fmax of 275 and 400 GHz at VDS = 0.5 V, which is the largest combined ft and fmax, as well as the largest fmax reported for all III-V MOSFETs.
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| 9. |
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| 10. |
- Passlack, M., et al.
(author)
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Core-shell tfet developments and tfet limitations
- 2019
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In: 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. - 9781728109428
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Conference paper (peer-reviewed)abstract
- Tunneling field-effect transistors (TFET) based on a vertical gate-All-Around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current \mathrm{I}-{\mathrm{o}\mathrm{n}} of 6.7\ \mu \mathrm{A} (NW diameter \mathrm{d}= 10.2\ \mathrm{nm}) at \mathrm{V}-{\mathrm{dd}}=0.3\ \mathrm{V} under low power (LP) conditions (\mathrm{I}-{\mathrm{off}}=1 \mathrm{pA}) for an InAs/GaSb CS TFET. This compares to Si nMOSFET \mathrm{I}-{\mathrm{on}} =2.3\ \mu \mathrm{A} at \mathrm{V}-{\mathrm{dd}}=0.55\ \mathrm{V}(\mathrm{d}=6\ \mathrm{nm}). On the experimental side, scaling of vertical CS NWs resulted in smallest dimensions of \mathrm{d}-{\mathrm{c}}= 17 nm (GaSb core) and \mathrm{t}-{\mathrm{sh}}=3 nm (InAs shell) for a total diameter of 23 nm. VGAA CS nFETs demonstrated drive current of up to 40\ \mu \mathrm{A} (\mathrm{V}-{\mathrm{d}}=0.3\ \mathrm{V}) and subthreshold swing \mathrm{SS}=40\mathrm{mV}/\mathrm{dec}(\mathrm{V}-{\mathrm{d}}=10\mathrm{mV}) for NW diameters between 35-50 nm. Although key TFET properties such as current drive and subthermal SS have been demonstrated using a VGAA CS architecture for the first time, experimental results still lag predictions. An intrinsic relationship between band-To band-Tunneling (BTBT) and \mathrm{D}-{\mathrm{it}} related trap assisted tunneling (TAT) was found which imposes challenging \mathrm{D}-{\mathrm{it}} requirements, in particular for LP \mathrm{I}-{\mathrm{off}} specifications. Complexity of fabrication and a material system foreign to CMOS manufacturing further impact prospects of TFET technology.
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| 11. |
- Vasen, T., et al.
(author)
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Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
- 2019
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In: Scientific Reports. - : Springer Science and Business Media LLC. - 2045-2322. ; 9:1
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Journal article (peer-reviewed)abstract
- Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.
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