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A single-cycle outp...
A single-cycle output buffered router with layered switching for Networks-on-Chips
- Article/chapterEnglish2012
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Elsevier BV,2012
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printrdacarrier
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LIBRIS-ID:oai:DiVA.org:kth-100612
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https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-100612URI
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https://doi.org/10.1016/j.compeleceng.2012.02.018DOI
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Language:English
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Summary in:English
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Subject category:ref swepub-contenttype
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Subject category:art swepub-publicationtype
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QC 20120813
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We present a single-cycle output buffered router based on layered switching for networks on chips (NoCs). Different from state-of-the-art NoC routers, the router has three important characteristics: (1) It employs layered switching, which implements wormhole on top of virtual cut-through (VCT) switching; (2) In contrast to input buffered architectures, it adopts an output buffered architecture; (3) It is single cycle, meaning that the router pipeline takes only one cycle for all flits. Experimental results show that the router achieves up to 80% of ideal network throughput under uniform random traffic pattern. Compared with wormhole switching, layered switching achieves up to 36.9% latency reduction for 12-flit packets under uniform random traffic with an injection rate of 0.5 flit/cycle/node. Under 65 nm technology synthesized results show that its critical path has only 20 logic gates, and it reduces 11% area compared to the input virtual-channel router with the same buffer capacity.
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Lu, ZhonghaiKTH,Elektroniksystem(Swepub:kth)u1wqy6h0
(author)
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Xie, Lunguo
(author)
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Li, Jinwen
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Zhang, Minxuan
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KTHElektroniksystem
(creator_code:org_t)
Related titles
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In:Computers & electrical engineering: Elsevier BV38:4, s. 906-9160045-79061879-0755
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