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- Navas, ByronKTH,Elektroniksystem (author)
The RecoBlock SoC Platform : A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks
- Article/chapterEnglish2013
Publisher, publication year, extent ...
- 2013
- printrdacarrier
Numbers
- LIBRIS-ID:oai:DiVA.org:kth-121778
- https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-121778URI
- https://doi.org/10.7873/DATE.2013.176DOI
Supplementary language notes
- Language:English
- Summary in:English
Part of subdatabase
- SwePubSwePub
Classification
Notes
- QC 20130822
- Run-time reconfigurable (RTR) FPGAs combine the flexibility of software with the high efficiency of hardware. Still, their potential cannot be fully exploited due to increased complexity of the design process. Consequently, to enable an efficient design flow, we devise a set of prerequisites to increase the flexibility and reusability of current FPGA-based RTR architectures. We apply these principles to design and implement the RecoBlock SoC platform, which main characterization is (1) a RTR plug-and-play IP-Core whose functionality is configured at run-time; (2) flexible inter-block communication configured via software, and (3) built-in buffers to support data-driven streams and inter-process communications. We illustrate the potential of our platform by a tutorial case study using an adaptive streaming application to investigate different combinations of reconfigurable arrays and schedules. The experiments underline the benefits of the platform and shows resource utilization.
Subject headings and genre
- TEKNIK OCH TEKNOLOGIER Elektroteknik och elektronik Inbäddad systemteknik hsv//swe
- ENGINEERING AND TECHNOLOGY Electrical Engineering, Electronic Engineering, Information Engineering Embedded Systems hsv//eng
- TEKNIK OCH TEKNOLOGIER Elektroteknik och elektronik Annan elektroteknik och elektronik hsv//swe
- ENGINEERING AND TECHNOLOGY Electrical Engineering, Electronic Engineering, Information Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering hsv//eng
- reconfigurable architectures
- partial and run-time reconfiguration
- system-on-chip
- adaptivity
- embedded systems
Added entries (persons, corporate bodies, meetings, titles ...)
- Sander, IngoKTH,Elektroniksystem(Swepub:kth)u1l8osh2 (author)
- Öberg, JohnnyKTH,Elektroniksystem(Swepub:kth)u1t0l5al (author)
- KTHElektroniksystem (creator_code:org_t)
Related titles
- In:Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, s. 833-8389781467350716
Internet link
- http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6513622&matchBoolean%3Dtrue%26searchField%3DSearch_All%26queryText%3D%28p_Title%3AThe+RecoBlock+SoC+Platform%3A+A+Flexible+Array+of+Reusable+Run-Time-Reconfigurable+IP-Blocks%29IEEEXplore
- https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-121778
- https://doi.org/10.7873/DATE.2013.176
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