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Concept and design ...
Concept and design of exhaustive-parallel search algorithm for Network-on-Chip
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Deivasigamani, M. (författare)
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- Tabatabaei, Shaghayeghsadat (författare)
- KTH,Elektroniksystem
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- Mustafa, Naveed Ul (författare)
- KTH,Elektroniksystem
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- Ijaz, Hamza (författare)
- KTH,Elektroniksystem
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- Aslam, Haris Bin (författare)
- KTH,Elektroniksystem
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- Liu, Shaoteng (författare)
- KTH,Elektroniksystem
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- Jantsch, Axel (författare)
- KTH,Elektroniksystem
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(creator_code:org_t)
- 2011
- 2011
- Engelska.
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Ingår i: Int. Syst. Chip Conf.. - 9781457716164 ; , s. 150-155
- Relaterad länk:
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http://web.it.kth.se...
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 88 mesh architecture and its performance is evaluated.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- Circuit-switch (CS)
- Exhaustive Parallel Search (EPS)
- Guaranteed Throughput (GT)
- Network-on-Chip (NoC)
- Guaranteed throughputs
- High performance switches
- Mesh architecture
- Minimal path
- Network on chip
- Parallel search
- Search Algorithms
- Learning algorithms
- Microprocessor chips
- Servers
- VLSI circuits
- Programmable logic controllers
Publikations- och innehållstyp
- ref (ämneskategori)
- kon (ämneskategori)
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