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High throughput arc...
High throughput architecture for OCTAGON network on chip
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Abd Elghany, M. A. (author)
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El-Moursy, M. A. (author)
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Korzec, D. (author)
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- Ismail, Mohammed (author)
- KTH,Integrerade komponenter och kretsar,Ohio State University, United States,RaMSiS Group
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(creator_code:org_t)
- IEEE, 2009
- 2009
- English.
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In: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - : IEEE. - 9781424450916 ; , s. 101-104
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Subject headings
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- High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- Latency
- Noc
- OCTAGON
- Throughput
Publication and Content Type
- ref (subject category)
- kon (subject category)
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