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High throughput arc...
High throughput architecture for high performance NoC
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Abd El Ghany, M. A. (author)
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El-Moursy, M. A. (author)
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- Ismail, Mohammed (author)
- KTH,Elektroniksystem,Ohio State University, Columbus, United States,RaMSiS Group
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(creator_code:org_t)
- IEEE, 2009
- 2009
- English.
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In: ISCAS. - : IEEE. - 9781424438280 ; , s. 2241-2244
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Subject headings
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- High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.
Subject headings
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Sciences (hsv//eng)
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- BFT
- Latency
- NoC
- Throughput
Publication and Content Type
- ref (subject category)
- kon (subject category)
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