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Fabrication of Nano...
Fabrication of Nanowires
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Bolten, J. (author)
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- Hellström, Per-Erik (author)
- KTH,Integrerade komponenter och kretsar
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- Östling, Mikael (author)
- KTH,Integrerade komponenter och kretsar
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Ternon, C. (author)
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Serre, P. (author)
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(creator_code:org_t)
- 2014-06-03
- 2014
- English.
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In: Beyond CMOS Nanodevices 1. - Hoboken, NJ, USA : Wiley Blackwell. - 9781118984772 - 9781848216549 ; , s. 5-23
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
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- Several fabrication processes of silicon nanowires have been developed in the research community. They can be divided into bottom-up or top-down approaches. This chapter describes top-down fabrication of silicon nanowires using electron beam lithography (EBL), which combined with optical lithography can be a viable approach if not too many silicon nanowires need to be patterned on a wafer. It also describes the sidewall transfer lithography (STL) technique using I-line stepper lithography to pattern a vast amount of silicon nanowires on a silicon wafer. In addition the chapter examines how bottom-up Si nanowires synthesized by vapor-liquid-solid (VLS)-chemical vapor deposition (CVD) can be assembled at low cost in an efficient way for further use as a sensing material. Among the solution-based assembly methods for the nanostructured network (nanonet) fabrication, the vacuum filtration method is highly simple, versatile, low cost and scalable to large areas.
Subject headings
- NATURVETENSKAP -- Kemi -- Materialkemi (hsv//swe)
- NATURAL SCIENCES -- Chemical Sciences -- Materials Chemistry (hsv//eng)
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
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- vet (subject category)
- kap (subject category)
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