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Dependable Multicore Architectures at Nanoscale : The View From Europe

Ottavi, Marco (author)
Pontarelli, S. (author)
Gizopoulos, D. (author)
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Bolchini, C. (author)
Michael, M. K. (author)
Anghel, L. (author)
Tahoori, M. (author)
Paschalis, A. (author)
Reviriego, P. (author)
Bringmann, O. (author)
Izosimov, Viacheslav (author)
Semcon, Sweden
Manhaeve, H. (author)
Strydis, C. (author)
Hamdioui, S. (author)
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 (creator_code:org_t)
IEEE, 2015
2015
English.
In: IEEE Design & Test. - : IEEE. - 2168-2356. ; 32:2, s. 17-28
  • Journal article (peer-reviewed)
Abstract Subject headings
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  • The introduction of multicore chips allowed the constant increase in delivered performance otherwise impossible to achieve. Multiple microprocessor cores from different instruction set architectures stay at the epicenter of such chips and are surrounded by memory cores of different technologies, sizes and functionalities, as well as by peripheral controllers, special function cores, analog and mixed-signal cores, reconfigurable cores, etc. The functionality as well as the complexity of multicore chips is unprecedented.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Maskinteknik (hsv//swe)
ENGINEERING AND TECHNOLOGY  -- Mechanical Engineering (hsv//eng)

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