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Accelerated On-chip...
Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model
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Karimi, E. (author)
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Haghbayan, M. -H (author)
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- Rahmani, Amir (author)
- KTH,Industriell och Medicinsk Elektronik
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Tabandeh, M. (author)
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Liljeberg, P. (author)
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Navabi, Z. (author)
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(creator_code:org_t)
- Institute of Electrical and Electronics Engineers (IEEE), 2015
- 2015
- English.
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In: Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479986699 ; , s. 283-288
- Related links:
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http://www.mcsoc-for...
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Subject headings
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- A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)
Keyword
- AMBA bus
- Complementary graph
- Fault model
- SoC
- State graph
- Buses
- Graphic methods
- Programmable logic controllers
- System-on-chip
- Extensive simulations
- Graph-based techniques
- High-level fault models
- On chip communication
- State graphs
- Testing
Publication and Content Type
- ref (subject category)
- kon (subject category)
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