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Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model

Karimi, E. (author)
Haghbayan, M. -H (author)
Rahmani, Amir (author)
KTH,Industriell och Medicinsk Elektronik
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Tabandeh, M. (author)
Liljeberg, P. (author)
Navabi, Z. (author)
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 (creator_code:org_t)
Institute of Electrical and Electronics Engineers (IEEE), 2015
2015
English.
In: Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479986699 ; , s. 283-288
  • Conference paper (peer-reviewed)
Abstract Subject headings
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  • A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)
ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)

Keyword

AMBA bus
Complementary graph
Fault model
SoC
State graph
Buses
Graphic methods
Programmable logic controllers
System-on-chip
Extensive simulations
Graph-based techniques
High-level fault models
On chip communication
State graphs
Testing

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Karimi, E.
Haghbayan, M. -H
Rahmani, Amir
Tabandeh, M.
Liljeberg, P.
Navabi, Z.
About the subject
ENGINEERING AND TECHNOLOGY
ENGINEERING AND ...
and Electrical Engin ...
and Computer Systems
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Proceedings - IE ...
By the university
Royal Institute of Technology

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