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A high-speed low-power divide-by-15/16 dual modulus prescaler in 0.6 mu m CMOS

Tang, Y. W. (author)
Aktas, A. (author)
Ismail, Mohammed (author)
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Bibyk, S. (author)
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2001
2001
English.
In: Analog Integrated Circuits and Signal Processing. - 0925-1030 .- 1573-1979. ; 28:2, s. 195-200
  • Journal article (peer-reviewed)
Abstract Subject headings
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  • A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 mum standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.

Keyword

frequency synthesizer
phase locked loop
dual modulus prescaler

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ref (subject category)
art (subject category)

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