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Non-blocking BIST f...
Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip
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Wang, J. (author)
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Huang, L. (author)
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Ebrahimi, M. (author)
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Li, Q. (author)
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Li, G. (author)
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- Jantsch, Axel (author)
- KTH,Elektronik,University of Electronic Science and Technology of China, China
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(creator_code:org_t)
- Institute of Electrical and Electronics Engineers (IEEE), 2017
- 2017
- English.
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In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467368520
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Subject headings
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- To achieve high reliability in on-chip networks, frequent runs of Built-in Self-Test allow the detection of and recovery from faults before they affect packets and the system functionality. However, to test routers, wrappers isolate cores from the network which leads to execution blocking and performance loss. In this paper, we propose a design-for-test reconfigurable router with two alternative bypassing channels. The router architecture allows maintaining the connection between cores and the network during the testing procedure by utilizing the bypassing channels. With the help of an adaptive routing algorithm and a testing strategy, networks can be fully tested at a high testing frequency with <15% increase of execution time.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Annan teknik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Other Engineering and Technologies (hsv//eng)
Publication and Content Type
- ref (subject category)
- kon (subject category)
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