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Synthesis of VLIW a...
Synthesis of VLIW accelerators from formal descriptions in a real-time multi-core environment
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- Öberg, Johnny (author)
- KTH,Elektronik
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(creator_code:org_t)
- 2017-09-19
- 2017
- English.
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In: 14th FPGAworld Conference, FPGAworld 2017 - Academic Proceedings 2017. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450351546 ; , s. 23-29
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
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- Designing, programming and design space exploration of predictable Real-Time systems on Heterogeneous Multi-Core platforms is a very complex task. The increasing validation costs and time-to-market pressure creates a desire to build systems that are correct by construction. Formal description based on Model of Computations (MoCs) is a convenient way to create high-level models of such systems. The MoCs provide abstraction and high level modeling through a clear set of rules based on mathematics, which can be used as input for system synthesis. A formal synthesis flow would then ensure that the resulting real-time system is both predictable and correct by construction, provided that all transformations used in the flow can be verified/trusted. In this paper we show how a Real-Time computation node in an MPSoC system, described using the Synchronous MoC, can be transformed into a VLIW accelerator. The created accelerator is incorporated as a computation node in a heterogeneous multi-core system implemented on an FPGA.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Inbäddad systemteknik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Embedded Systems (hsv//eng)
Publication and Content Type
- ref (subject category)
- kon (subject category)
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