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A Trace-driven Hard...
A Trace-driven Hardware-level Simulator for Design and Verification of Network-on-Chips
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- Chen, Yancang (author)
- Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China.
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- Xie, Lunguo (author)
- Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China.
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- Li, Jinwen (author)
- Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China.
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- Shi, Zhu (author)
- Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China.
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- Zhang, Minxuan (author)
- Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China.
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- Chen, Xiaowen (author)
- Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China.
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- Lu, Zhonghai (author)
- KTH,Elektronik och inbyggda system
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Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China Elektronik och inbyggda system (creator_code:org_t)
- IEEE, 2010
- 2010
- English.
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In: 2011 INTERNATIONAL CONFERENCE ON COMPUTERS, COMMUNICATIONS, CONTROL AND AUTOMATION (CCCA 2011), VOL II. - : IEEE. ; , s. 32-35
- Related links:
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https://urn.kb.se/re...
Abstract
Subject headings
Close
- Traditional communications of general-purpose multi-core processor and application-specific System-on-Chip face challenges in terms of scalability and complexity. Network-on-Chip (NoC) has been the most promising solution for the communications of multi-core and many-core chips. In this paper, we present a trace-driven hardware-level simulator (noted HS) based on SystemVerilog for the design and verification of NoCs. Different from the state-of-the-art NoC simulators, the HS owns three important characteristics in addition to the capability of creating simulation and synthesizable NoC descriptions: 1) hardware-level simulation can be done, which means more implementation details of hardware than flit-level simulation; 2) router debugging and verification can be done at RTL by inserting assertions and coverage; 3) trace-based application simulations can be done besides synthetic workloads. A 4 X 4 2D mesh NoC with output virtual-channel routers verifies the capability of our HS.
Subject headings
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
Keyword
- Network-on-Chips
- Hardware-level Simulation
- SystemVerilog
- Verification
Publication and Content Type
- ref (subject category)
- kon (subject category)
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