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Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer
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- Zurauskaite, Laura (author)
- KTH,Elektronik och inbyggda system
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- Hellström, Per-Erik, 1970- (author)
- KTH,Elektronik och inbyggda system
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- Östling, Mikael (author)
- KTH,Elektronik och inbyggda system
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(creator_code:org_t)
- 2020-12-29
- 2020
- English.
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In: ECS Journal of Solid State Science and Technology. - : The Electrochemical Society. - 2162-8769 .- 2162-8777. ; 9:12
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Abstract
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- In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 degrees C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for D-it < 510(11) cm(-2) eV(-1). Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 310(11) eV(-1) cm(-2) and a significant improvement in oxide trap density compared to GeOx passivation.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Publication and Content Type
- ref (subject category)
- art (subject category)
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