A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash

• For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve attractive trade off between implementation complexity and decoding performance. In this paper, a novel low bit-width decoding scheme is introduced. In this scheme, the Quasi-Cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower UBER (Uncorrectable Bit Error Rate) with a negligible increase in computational complexity, especially with low precision input log-likelihood ratio (LLR).

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Telekommunikation (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Telecommunications (hsv//eng)

Keyword

bit-width.

Decoding

Error correction

Hardware

Iterative decoding

low-density parity-check (LDPC) codes

Manganese

min-sum decoding

NAND flash memory

Reliability

Throughput

Bit error rate

Economic and social effects

Flash memory

Memory architecture

NAND circuits

Decoding algorithm

Decoding performance

Implementation complexity

Log likelihood ratios (LLR)

Low density parity check decoding

Normalized min-sum algorithms

Quasi-cyclic LDPC (QC-LDPC)

Uncorrectable bit error rates

Publication and Content Type

ref (subject category)

art (subject category)