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Temporal Logic Trees for Model Checking and Control Synthesis of Uncertain Discrete-time Systems

Gao, Yulong (author)
KTH,Reglerteknik
Abate, Alessandro (author)
Department of Computer Science, University of Oxford, Oxford, United Kingdom, OX1 3QD
Jiang, Frank (author)
KTH,Reglerteknik
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Giacobbe, Mirco (author)
Department of Computer Science, University of Oxford, Oxford, United Kingdom, OX1 3QD
Xie, Lihua (author)
School of Elect. & Electr. Eng., BLK S2, Nanyang Tech. Univ., Singapore, Singapore, Singapore, 639798
Johansson, Karl H., 1967- (author)
KTH,Reglerteknik
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 (creator_code:org_t)
Institute of Electrical and Electronics Engineers (IEEE), 2021
2021
English.
In: IEEE Transactions on Automatic Control. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9286 .- 1558-2523. ; , s. 1-1
  • Journal article (peer-reviewed)
Abstract Subject headings
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  • We propose algorithms for performing model checking and control synthesis for discrete-time uncertain systems under linear temporal logic (LTL) specifications. We construct temporal logic trees (TLT) from LTL formulae via reachability analysis. In contrast to automaton-based methods, the construction of the TLT is abstraction-free for infinite systems, that is, we do not construct discrete abstractions of the infinite systems. Moreover, for a given transition system and an LTL formula, we prove that there exist both a universal TLT and an existential TLT via minimal and maximal reachability analysis, respectively. We show that the universal TLT is an underapproximation for the LTL formula and the existential TLT is an overapproximation. We provide sufficient conditions and necessary conditions to verify whether a transition system satisfies an LTL formula by using the TLT approximations. As a major contribution of this work, for a controlled transition system and an LTL formula, we prove that a controlled TLT can be constructed from the LTL formula via control-dependent reachability analysis. Based on the controlled TLT, we design an online control synthesis algorithm, under which a set of feasible control inputs can be generated at each time step. We also prove that this algorithm is recursively feasible. We illustrate the proposed methods for both finite and infinite systems and highlight the generality and online scalability with two simulated examples.

Subject headings

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)
NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Sciences (hsv//eng)

Keyword

Automata
Control systems
Linear systems
Model checking
Reachability analysis
Trajectory
Uncertainty
Abstracting
Computer circuits
Control system synthesis
Digital control systems
Discrete time control systems
Forestry
Online systems
Trees (mathematics)
Uncertainty analysis
Automaton
Control synthesis
Infinite system
Linear temporal logic
Logic tree
Models checking
Temporal logic formula
Transition system
Temporal logic

Publication and Content Type

ref (subject category)
art (subject category)

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