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3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide
- Kobayashi, M. (author)
- Uchida, H. (author)
- Minami, A. (author)
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- Sakata, A. (author)
- Esteve, Romain (author)
- Schöner, A. (author)
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- 2011
- 2011
- English.
- In: Materials Science Forum. - 0255-5476 .- 1662-9752. ; 679-680, s. 645-648
- Journal article (peer-reviewed)
Abstract
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- 3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.
Keyword
- 3C-SiC
- Capacitance-Voltage Characteristics
- Channel Mobility
- CVD Deposited Oxide
- MOSFET
- On Resistance
- Post Oxidation Annealing
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- art (subject category)
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- Kobayashi, M.
- Uchida, H.
- Minami, A.
- Sakata, A.
- Esteve, Romain
- Schöner, A.
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- Royal Institute of Technology
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