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Heterogeneous Recon...
Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data
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- Song, Wenqing (author)
- Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Peoples R China.
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- Shen, Sirui (author)
- Ctr Wiskunde & Informat CWI Amsterdam, NL-1098 XG Amsterdam, Netherlands.
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- Xu, Congwei (author)
- Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Peoples R China.
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- Wang, Yilin (author)
- Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Peoples R China.
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- Wang, Xinyu (author)
- Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Peoples R China.
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- Fu, Yuxiang (author)
- Nanjing Univ, Sch Integrated Circuit, Nanjing 210023, Peoples R China.
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- Li, Li (author)
- Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Peoples R China.
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- Lu, Zhonghai (author)
- KTH,Elektronik och inbyggda system
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Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Peoples R China Ctr Wiskunde & Informat CWI Amsterdam, NL-1098 XG Amsterdam, Netherlands. (creator_code:org_t)
- Institute of Electrical and Electronics Engineers (IEEE), 2024
- 2024
- English.
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In: IEEE Access. - : Institute of Electrical and Electronics Engineers (IEEE). - 2169-3536. ; 12, s. 11850-11864
- Related links:
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https://doi.org/10.1...
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https://urn.kb.se/re...
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Abstract
Subject headings
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- Homomorphic encryption (HE) enables third -party servers to perform computations on encrypted user data while preserving privacy. Although conceptually attractive, the speed of software implementations of HE is almost impractical. To address this challenge, various domain -specific architectures have been proposed to accelerate homomorphic evaluation, but efficiency remains a bottleneck. In this paper, we propose a homomorphic evaluation accelerator with heterogeneous reconfigurable modular computing units (RCUs) for the Brakerski/Fan-Vercauteren (BFV) scheme. RCUs leverage operator abstraction to efficiently perform basic sub -operations of homomorphic evaluation such as residue number system (RNS) conversion, number theoretic transform (NTT), and other modular computations. By combining these sub -operations, complex homomorphic evaluation operations like multiplication, rotation, and addition are efficiently executed. To address the high demand for data access and improve memory efficiency, we design a coordinate -based address encoding strategy that enables in -place and conflict -free data access. Furthermore, specific optimizations are performed on the core sub -operations such as NTT and automorphism. The proposed architecture is implemented on Xilinx Virtex-7 and UltraScale+ FPGA platforms and evaluated for polynomials of length 4096. Compared to state-of-the-art accelerators with the same parameter set, our accelerator achieves the following advantages: 1) 2.04x to 3.33x reduction in the area -time product (ATP) for the key sub -operation NTT, 2) 1.08x to 7.42x reduction in latency for homomorphic multiplication with higher area efficiency, and 3) support for a wider range of homomorphic evaluation operations, including rotation, compared to other BFV-based accelerators.
Subject headings
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
Keyword
- BFV
- hardware acceleration
- homomorphic encryption
- number theoretic transform
Publication and Content Type
- ref (subject category)
- art (subject category)
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