Non-planar devices for nanoscale CMOS

• In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and rnanufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Nanoteknik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Nano-technology (hsv//eng)

Keyword

SOI

FinFET

tri-gate

triple gate

nano-CMOS

nanowire

Publication and Content Type

ref (subject category)

kon (subject category)