Search: onr:"swepub:oai:DiVA.org:kth-63609" >
An Analytical Laten...
An Analytical Latency Model for Networks-on-Chip
-
- Eslami Kiasari, Abbas (author)
- KTH,Elektroniksystem
-
- Lu, Zhonghai (author)
- KTH,Elektroniksystem
-
- Jantsch, Axel (author)
- KTH,Elektroniksystem
-
(creator_code:org_t)
- 2013
- 2013
- English.
-
In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210 .- 1557-9999. ; 21:1, s. 113-123
- Related links:
-
https://urn.kb.se/re...
-
show more...
-
https://doi.org/10.1...
-
show less...
Abstract
Subject headings
Close
- We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed model takes as input an application communication graph, a topology graph, a mapping vector, and a routing matrix, and estimates average packet latency and router blocking time. It works for arbitrary network topology with deterministic routing under arbitrary traffic patterns. This model can estimate per-flow average latency accurately and quickly, thus enabling fast design space exploration of various design parameters in NoC designs. Experimental results show that the proposed analytical model can predict the average packet latency more than four orders of magnitude faster than an accurate simulation, while the computation error is less than 10% in non-saturated networks for different system-on-chip platforms.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Keyword
- Modeling and prediction
- network-on-chip (NoC)
- performance analysis and design aids
- queueing theory
Publication and Content Type
- ref (subject category)
- art (subject category)
Find in a library
To the university's database