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Implementation of a...
Implementation of a scalable, globally plesiochronous locally synchronous, off-chip NoC communication protocol
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- Minhass, Wajid Hassan (author)
- KTH,Elektronik- och datorsystem, ECS
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- Öberg, Johnny (author)
- KTH,Elektronik- och datorsystem, ECS
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- Sander, Ingo, 1964- (author)
- KTH,Elektronik- och datorsystem, ECS
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(creator_code:org_t)
- 2009
- 2009
- English.
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In: 2009 NORCHIP. - 9781424443109 ; , s. 1-5
- Related links:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
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- Multiprocessor system-on-chip design (MPSoC) is becoming a regular feature of the embedded systems. Shared-bus systems hold many advantages, but they do not scale. Network on chip (NoC) offers a promising solution to the scalability problem by enhancing the topology design. However, standard NoCs are only scalable within a chip. To be able to build infinitely scalable structures, a method to enhance the NoC-grid off-chip is needed. In this paper, we present such a method. As a proof of concept, the protocol is implemented on a 4 by 4 Mesh NoC, with NIOS II CPU cores as nodes, partitioned across four separate Altera FPGA boards, each board hosting a Quad-Core (2x2) NoC, operating on a local 50 MHz clock. The inter-chip communication protocol uses asynchronous clock bridges, with a throughput of 50 Mbps (~1MFlit/s) and is completely scalable. The NoC has an onboard throughput of 650 Mbps (12.5 MFlit/s). Each Quad-Core uses 28% of the LUs, 18% of the ALUTs, 22 % of the dedicated registers and 31% of the total memory blocks of the Stratix II FPGAs. Application programs use an MPI compatible Hardware Abstraction Layer (HAL) to communicate with each other over the NoC.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Inbäddad systemteknik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Embedded Systems (hsv//eng)
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- kon (subject category)
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