System level virtual prototyping of DSP ASICs using grammar based approach

• DSP systems are often modeled using functional and bit-true level simulators, where it is not possible to validate the system level timing, control and configuration (SLTCC) of the product. In this paper, we present a methodology that adds SLTCC specified in grammar to functional models to create a rate true system level virtual prototype. The methodology is illustrated and benefits are quantified using two realistic examples

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

DSP ASICs;bit-true level simulators;control and configuration;grammar based approach;system level timing;system level virtual prototype;system level virtual prototyping;application specific integrated circuits;computational complexity;digital signal processing chips;software prototyping;timing

Publication and Content Type

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