Hardware synthesis of an ATM multiplexer from SDL to VHDL : a case study

• Hardware synthesis of SDL models poses several problems, because SDL uses Communicating Sequential Processes (CSP) paradigm for system specification. It allows dynamic processes and its semantics assume an infinite FIFO buffer at the input of each process for inter-process communication. We had presented previously a methodology and later refined it for efficient hardware synthesis from SDL specification. In this paper we describe the experience of applying this methodology to a large case study. The case study is an ATM Multiplexer which exhibits a complex control flow and uses large tables. It was modelled using multiple processes. Hardware synthesis was carried out using the methodology starting from its SDL model. The results show that the methodology leads to a correct and efficient hardware implementation. In particular, the methodology avoids use of costly FIFO buffers for implementing inter-process communication and allows sharing of hardware resources among various instances of the same process. The final implementation also meets the 155 Mbit/sec data rate performance requirement

Subject headings

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Keyword

155 Mbit/s;ATM multiplexer;Communicating Sequential Processes;FIFO buffers;SDL;VHDL;dynamic processes;hardware synthesis;infinite FIFO buffer;inter-process communication;system specification;asynchronous transfer mode;communicating sequential processes;hardware description languages;logic CAD;multiplexing equipment;specification languages;telecommunication computing

Publication and Content Type

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