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A 5 GHz floating point multiply-accumulator in 90 nm dual VT CMOS
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- Vangal, Sriram (author)
- Linköpings universitet,Institutionen för systemteknik,Tekniska högskolan
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- Hoskote, Yatin (author)
- Microprocessor Research Labs, Intel, Hillsboro, OR, USA
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- Somasekhar, Dinesh (author)
- Microprocessor Research Labs, Intel, Hillsboro, OR, USA
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- (creator_code:org_t)
- IEEE, 2003
- 2003
- English.
- In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers. - : IEEE. - 0780377079 ; , s. 334-335
- Conference paper (peer-reviewed)
Abstract
Subject headings
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- A 32 b single-cycle floating point accumulator that uses base 32 and carry-save format with delayed addition is described. Combined algorithmic, logic and circuit techniques enable multiply-accumulate operation at 5 GHz. In a 90 nm 7M dual-VT CMOS process, the 2 mm2 prototype contains 230K transistors and dissipates 1.2 W at 5 GHz, 1.2 V and 25°C.
Keyword
- TECHNOLOGY
- TEKNIKVETENSKAP
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- kon (subject category)
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